2009 International Conference on High Performance Switching and Routing最新文献_第3页

A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2 基于动态可重构处理器DAPDNA-2的片上立体网络流量工程新方法

2009 International Conference on High Performance Switching and Routing Pub Date : 2009-06-22 DOI: 10.1109/HPSR.2009.5307432

Shan Gao, T. Kihara, S. Shimizu, Y. Arakawa, N. Yamanaka, Akifumi Watanabey

引用次数: 3

Packet processing with blocking for bursty traffic on multi-thread network processor 多线程网络处理器上突发流量的分组阻塞处理

2009 International Conference on High Performance Switching and Routing Pub Date : 2009-06-22 DOI: 10.1109/HPSR.2009.5307419

Yeim-Kuan Chang, Fang-Chen Kuo

{"title":"Packet processing with blocking for bursty traffic on multi-thread network processor","authors":"Yeim-Kuan Chang, Fang-Chen Kuo","doi":"10.1109/HPSR.2009.5307419","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307419","url":null,"abstract":"It is well-known that there are bursty accesses in network traffic. It means a burst of packets with the same meaningful headers are usually received by routers at the same time. With such traffic, routers usually perform the same computations and access the same memory location repeatedly. To utilize this characteristic of network traffic, many cache schemes are proposed to deal with the bursty access patterns. However, in the multi-thread network processor based routers, the existing cache schemes will not suit to the bursty traffic. Since all threads may all deal with the packets with the same headers, if the former threads do not update the cache entries yet, the subsequent threads still have to repeat the computations due to the cache miss. In this paper, we propose a cache scheme called B-cache for the multi-thread network processors. B-cache blocks the subsequent threads from doing the same computations which are being processed by the former thread. By applying B-cache, any packet processing tasks with high locality characteristic, such as IP address lookup, packet classification, and intrusion detection, can avoid the duplicate computations and hence achieve a better packet processing rate. We implement the proposed B-cache scheme on Intel IXP2400 network processor, the experimental results shows that our B-cache scheme can achieves the line speed of Intel IXP2400.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128525044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Scalability of ROADMs for multiple parallel fibers 多平行光纤roadm的可扩展性

2009 International Conference on High Performance Switching and Routing Pub Date : 2009-06-22 DOI: 10.1109/HPSR.2009.5307431

C. Meusburger, D. Schupke

引用次数: 0

Secure and scalable optical access network using PLZT high-speed optical switches 采用PLZT高速光交换机的安全、可扩展的光接入网

2009 International Conference on High Performance Switching and Routing Pub Date : 2009-06-22 DOI: 10.1109/HPSR.2009.5307433

Kazumasa Tokuhashi, Kunitaka Ashizawa, D. Ishii, Y. Arakawa, N. Yamanaka, K. Wakayama

引用次数: 23

Multicast scheduling in feedback-based two-stage switch 基于反馈的两级交换机组播调度

2009 International Conference on High Performance Switching and Routing Pub Date : 2009-06-22 DOI: 10.1109/HPSR.2009.5307438

Bing Hu, K. Yeung

{"title":"Multicast scheduling in feedback-based two-stage switch","authors":"Bing Hu, K. Yeung","doi":"10.1109/HPSR.2009.5307438","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307438","url":null,"abstract":"Scalability is of paramount importance in high-speed switch design. Two limiting factors are the complexity of switch fabric and the need for a sophisticated central scheduler. In this paper, we focus on designing a scalable multicast switch. Given the fact that the majority traffic on the Internet is unicast, a costeffective solution is to adopt a unicast switch fabric for handling both unicast and multicast traffic. Unlike existing approaches, we choose to base our multicast switch design on the load-balanced two-stage switch architecture because it does not require a central scheduler, and its unicast switch fabric only needs to realize N switch configurations. Specifically, we adopt the feedback-based two-stage switch architecture [10], because it elegantly solves the notorious packet mis-sequencing problem, and yet renders an excellent throughput-delay performance. By slightly modifying the operation of the original feedback-based two-stage switch, a simple distributed multicast scheduling algorithm is proposed. Simulation results show that with packet duplication at both input ports and middle-stage ports, the proposed multicast scheduling algorithm significantly cuts down the average packet delay and delay variation among different copies of the same multicast packet.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134017787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Adaptive routing for Convergence Enhanced Ethernet 增强收敛以太网的自适应路由

2009 International Conference on High Performance Switching and Routing Pub Date : 2009-06-22 DOI: 10.1109/HPSR.2009.5307439

C. Minkenberg, A. Scicchitano, M. Gusat

{"title":"Adaptive routing for Convergence Enhanced Ethernet","authors":"C. Minkenberg, A. Scicchitano, M. Gusat","doi":"10.1109/HPSR.2009.5307439","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307439","url":null,"abstract":"A significant drive to consolidate data center networks on a single infrastructure is taking place. 10-Gigabit Ethernet is one of the contenders to fulfill the role of universal data center interconnect. One of the key features missing from conventional Ethernet is congestion management; this void is being filled by the standardization work of the IEEE 802.1Qau working group. However, the schemes under consideration react to congestion only at the sources by reducing the transmission rates of “hot” flows, i.e., those detected as contributing to congestion. This approach ignores a crucial aspect of many data center networks, namely, that there typically are multiple paths between any pair of end nodes. Before reducing transmission rates, it would make sense to look for an alternative, uncongested path first. Here, we propose an adaptive routing scheme that builds—in a fully transparent way—on top of the existing 802.1Qau schemes, by snooping the congestion notification frames to modify the routing behavior of the switching nodes. We demonstrate how this can lead to significant performance improvements by taking full advantage of path diversity.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130490298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An implementation and experimental study of the Adaptive PI Rate Control Protocol 自适应PI速率控制协议的实现与实验研究

2009 International Conference on High Performance Switching and Routing Pub Date : 2009-06-22 DOI: 10.1109/HPSR.2009.5307424

Zhanliang Liu, Huan Wang, Wu Hu, Yang Hong, O. Yang, Y. Shu

引用次数: 7

Frugal IP lookup based on a parallel search 基于并行搜索的低成本IP查找

2009 International Conference on High Performance Switching and Routing Pub Date : 2009-06-22 DOI: 10.1109/HPSR.2009.5307435

Z. Čiča, A. Smiljanic

{"title":"Frugal IP lookup based on a parallel search","authors":"Z. Čiča, A. Smiljanic","doi":"10.1109/HPSR.2009.5307435","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307435","url":null,"abstract":"Lookup function in the IP routers has always been a topic of a great interest since it represents a potential bottleneck in improving Internet router's capacity. IP lookup stands for the search of the longest matching prefix in the lookup table for the given destination IP address. The lookup process must be fast in order to support increasing port bit-rates and the number of IP addresses. The lookup table updates must be also performed fast because they happen frequently. In this paper, we propose a new algorithm based on the parallel search implemented on the FPGA chip that finds the next hop information in the external memory. The lookup algorithm must support both the existing IPv4 protocol, as well as the future IPv6 protocol. We analyze the performance of the designed algorithm, and compare it with the existing lookup algorithms. Our proposed algorithm allows a fast search because it is parallelized within the FPGA chip. Also, it utilizes the memory more efficiently than other algorithms because it does not use the resources for the empty subtrees. The update process that the proposed algorithm performs is as fast as the search process. The proposed algorithm will be implemented and analyzed for both IPv4 and IPv6. It will be shown that it supports IPv6 effectively.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123559192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6