H. Yu, J. Kittl, A. Lauwers, R. Singanamalla, C. Demeurisse, S. Kubicek, E. Augendre, A. Veloso, S. Brus, C. Vrancken, T. Hoffmann, S. Mertens, B. Onsia, R. Verbeeck, M. Demand, A. Rothchild, B. Froment, M. V. van Dal, K. Meyer, M. Li, J.D. Chen, M. Jurczak, P. Absil, S. Biesemans
{"title":"Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-Based FUSI","authors":"H. Yu, J. Kittl, A. Lauwers, R. Singanamalla, C. Demeurisse, S. Kubicek, E. Augendre, A. Veloso, S. Brus, C. Vrancken, T. Hoffmann, S. Mertens, B. Onsia, R. Verbeeck, M. Demand, A. Rothchild, B. Froment, M. V. van Dal, K. Meyer, M. Li, J.D. Chen, M. Jurczak, P. Absil, S. Biesemans","doi":"10.1109/VLSIT.2006.1705235","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705235","url":null,"abstract":"This report discusses a new and practical approach to implement low Vt bulk CMOS using Ni-based FUSI MOSFETs. On the nFET, we demonstrate for the first time that incorporating Yb by ion implantation can achieve similar reduction of effective work function (WF) compared to alloying making it a candidate for CMOS integration. We complement our previous work on WF modulation by Yb on NiSi/SiON with new data on NiSi/HfSiON and NiGeSi/HfSiON. On the pFET, we study the effect of Al and Pt on Ni-rich FUSI and integrate it with a SiGe-channel. Integration into our reference devices resulted in a Vt reduction from 0.55/0.61V down to 0.30/0.25V for nFET (NiSi:Yb gate) and pFET (Ni2 Si:Pt gate + SiGe channel) respectively on SiON without degradation of the dielectric integrity and long channel mobility, and without an increase in gate leakage and Dit","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"9 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128519038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Huiling Shang, Leland Chang, Xinhui Wang, Michael J. Rooks, Y. Zhang, B. To, Katherina Babich, G. Totir, Yanning Sun, E. Kiewra, M. Ieong, Wilfried Haensch
{"title":"Investigation of FinFET Devices for 32nm Technologies and Beyond","authors":"Huiling Shang, Leland Chang, Xinhui Wang, Michael J. Rooks, Y. Zhang, B. To, Katherina Babich, G. Totir, Yanning Sun, E. Kiewra, M. Ieong, Wilfried Haensch","doi":"10.1109/VLSIT.2006.1705213","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705213","url":null,"abstract":"FinFET devices are demonstrated with multiple fins (>2) at a 120nm pitch using e-beam lithography to address some key challenges of FINFETs for 32nm node technologies and beyond. Target Vt's are achieved by proper halo design using 20nm fins. Vt scatter due to Fin width variation is greatly reduced with a reduced halo. When such a realistic fin pitch is used, S/D contact formation becomes a serious challenge due to poly-to-active overlay requirements and the need for raised S/D for series resistance reduction. A new FinFET design without S/D contact pads is thus proposed and a selective epitaxial process to merge individual fins is developed","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128240166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Kido, M. Kito, R. Katsumata, M. Kondo, S. Ito, K. Matsuo, K. Miyano, L. Mizushima, M. Sato, H. Tanaka, H. Yasutake, Y. Nagata, T. Hoshino, N. Aoki, H. Aochi, A. Nitayama
{"title":"Vertex Channel Field Effect Transistor (VC-FET) Technology Featuring High Performance and Highly Manufacturable Trench Capacitor DRAM","authors":"M. Kido, M. Kito, R. Katsumata, M. Kondo, S. Ito, K. Matsuo, K. Miyano, L. Mizushima, M. Sato, H. Tanaka, H. Yasutake, Y. Nagata, T. Hoshino, N. Aoki, H. Aochi, A. Nitayama","doi":"10.1109/VLSIT.2006.1705204","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705204","url":null,"abstract":"Vertex channel (VC) transistor is applied to both support devices and array transistor of trench capacitor DRAM for the first time. On-current of VC-FETs is much higher than that of conventional planar devices with keeping sufficiently small off-current. They achieve 15% or much smaller propagation delay (Tpd) of fan-out 3 than planar devices. Furthermore, 1.6 times of on-current as a planar array transistor is achieved by the combination of VCAT and P+poly gate without degradation of retention characteristics","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127043166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y.J. Song, K. Ryoo, Y. Hwang, C. Jeong, D. Lim, S.S. Park, J. Kim, J. Kim, S.Y. Lee, J. Kong, S. Ahn, S. Lee, J. Park, J. Oh, Y. Oh, J. Kim, J.M. Shin, Y. Fai, G. Koh, G. Jeong, R. Kim, H.S. Lim, I.S. Park, H. Jeong, Kinam Kim
{"title":"Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology","authors":"Y.J. Song, K. Ryoo, Y. Hwang, C. Jeong, D. Lim, S.S. Park, J. Kim, J. Kim, S.Y. Lee, J. Kong, S. Ahn, S. Lee, J. Park, J. Oh, Y. Oh, J. Kim, J.M. Shin, Y. Fai, G. Koh, G. Jeong, R. Kim, H.S. Lim, I.S. Park, H. Jeong, Kinam Kim","doi":"10.1109/VLSIT.2006.1705245","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705245","url":null,"abstract":"Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115858722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Jeong, D. Shin, A. Kim, Il Young Yoon, S.W. Nam, Seung-jin Lee, Ki-kwan Park, K.C. Kim, Hong-jae Shin, Ki bong Roh, K. Kang, Yong-ho Choi, Gi-ho Seo, Kwon–Woo Lee, K. Chu, N. Lee
{"title":"Pre-Metal Dielectric Stress Engineering by a Novel Plasma Treatment and Integration Scheme for nMOS Performance Improvement","authors":"Y. Jeong, D. Shin, A. Kim, Il Young Yoon, S.W. Nam, Seung-jin Lee, Ki-kwan Park, K.C. Kim, Hong-jae Shin, Ki bong Roh, K. Kang, Yong-ho Choi, Gi-ho Seo, Kwon–Woo Lee, K. Chu, N. Lee","doi":"10.1109/VLSIT.2006.1705254","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705254","url":null,"abstract":"For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O3-TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O3-TEOS films show more tensile stress value about twice than that of an as-deposited O3 -TEOS film. The novel process shows up to 10% improvement of Ion for nMOS without any cost of pMOS degradation","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131360351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Direct Non-Contact Electrical Measurement of Low-k Damage in Patterned Low-k Films by a Near-Field Scanned Microwave Probe","authors":"J.S. Tsai, J.W. Hsu, J. Shieh, S. Jang, M. Liang","doi":"10.1109/VLSIT.2006.1705242","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705242","url":null,"abstract":"We demonstrate a near-field scanned microwave probe and specific test keys for direct non-contact electrical measurement of low-k dielectric constant and damage after deposition, during trench/via processing, and after metallization. This work successfully defines the dielectric constant and the thickness of the damaged layer in patterned low-k films, and is the first demonstration of a metrology for electrical in-line measurements of low-k damage. Furthermore, we point out the integration issue of porous low-k by using this novel technique","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134349826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Oh, Sung Hwan Kim, N. Kim, Y. L. Choi, Yong Seok Lee, WonJun Jang, Hyo San Lee, H. Park, Dong-Won Kim, Donggun Park, B. Ryu
{"title":"A Novel Multi-Functional Silicon-On-ONO (SOONO) MOSFETs for SoC Applications: Electrical Characterization for High Performance Transistor and Embedded Memory Applications","authors":"C. Oh, Sung Hwan Kim, N. Kim, Y. L. Choi, Yong Seok Lee, WonJun Jang, Hyo San Lee, H. Park, Dong-Won Kim, Donggun Park, B. Ryu","doi":"10.1109/VLSIT.2006.1705210","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705210","url":null,"abstract":"We proposed and successfully demonstrate multi-functional Si-on-ONO (SOONO) MOSFETs. As a high performance transistor and embedded 2-bit flash memory, they show the reasonable characteristics. SOONO MOSFETs act as ultra thin body transistor with self-limited shallow junction, resulting in good SCE immunity and high driving currents, 737muA/mum for nMOS and 330muA/mum for pMOS at |VGS| = |VDS| = 1 V, IOFF = 100 nA/mum). In terms of flash memory, SOONO MOSFET acts as 2-bit flash memory with 2 physically separated storage node in back side. By using CHEI/HHI program/erase, each node was easily programmed and erased. In the gate length of 120 nm, we achieved the read/write margins of ~1.3 V at VDS = 1.2 V and the VTH shifts of ~2.5V for both program/erase","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131562428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Suk-kang Sung, Se-Hoon Lee, B. Choi, J. Lee, J. Choe, E. Cho, Y. Ahn, D. Choi, Choong-ho Lee, Dong Hyun Kim, Yong-Seok Lee, S. Kim, Donggun Park, B. Ryu
{"title":"SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory","authors":"Suk-kang Sung, Se-Hoon Lee, B. Choi, J. Lee, J. Choe, E. Cho, Y. Ahn, D. Choi, Choong-ho Lee, Dong Hyun Kim, Yong-Seok Lee, S. Kim, Donggun Park, B. Ryu","doi":"10.1109/VLSIT.2006.1705229","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705229","url":null,"abstract":"For the multi-gigabit NAND flash memory, SONOS-type FinFET device with p+ gate and high-k blocking dielectric has been integrated both on the cell array and GSL/SSL for the first time. The advantages of the FinFET structure for the NAND flash application have been theoretically and experimentally demonstrated, and the results show that the 85 % improved on-cell current is achievable using FinFET device. The enhanced programming and retention characteristics of FinFET have been also presented, and modeled by the potential changes on fully-depleted body of the sub-40 nm ultra-narrow fin","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132281256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ando, T. Hirano, K. Tai, S. Yamaguchi, T. Kato, Y. Hagimoto, K. Watanabe, R. Yamamoto, S. Kanda, K. Nagano, S. Terauchi, Y. Tateshita, Y. Tagawa, M. Saito, H. Iwamoto, S. Yoshida, H. Watanabe, N. Nagashima, S. Kadomura
{"title":"Sub-1nm EOT HfSix/HfO2 Gate Stack Using Novel Si Extrusion Process for High Performance Application","authors":"T. Ando, T. Hirano, K. Tai, S. Yamaguchi, T. Kato, Y. Hagimoto, K. Watanabe, R. Yamamoto, S. Kanda, K. Nagano, S. Terauchi, Y. Tateshita, Y. Tagawa, M. Saito, H. Iwamoto, S. Yoshida, H. Watanabe, N. Nagashima, S. Kadomura","doi":"10.1109/VLSIT.2006.1705269","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705269","url":null,"abstract":"Sub-1nm EOT and high electron mobility were realized at the same time with HfSi<sub>x</sub>/HfO<sub>2</sub> gate stacks. It was revealed that there exist two mobility degradation modes depending on the HfO<sub>2</sub> thickness and the HfSi<sub>x</sub> composition. One is the crystallization in the thick HfO<sub>2</sub> case (Tinv > 1.6 nm). The other is the Hf penetration into the interfacial layer with the Si substrate (bottom-IFL) in the thin HfO<sub>2</sub> case (Tinv < 1.6 nm) for the Hf-rich electrode. We have demonstrated that carefully optimizing the HfO<sub>2</sub> thickness and introducing a novel \"Si extrusion\" process from the HfSi<sub>x</sub> electrode can suppress both modes. As a result, a high electron mobility equivalent to n<sup>+</sup>poly-Si/SiO<sub>2</sub> (248 cm<sup>2</sup>/Vs @ Eeff = 1 MV/cm) was obtained at the sub-1nm EOT region for the very first time. The successful scaling together with a well-controlled Vth roll-off led to an extremely high Ion of 1165 muA/mum (@ Ioff = 81 nA/mu) at Vdd = 1.0V for a 45nm gate nMOSFET","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117162072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Nakamura, Y. Nakahara, N. Kimizuka, T. Abe, I. Yamamoto, T. Fukase, T. Nakayama, K. Taniguchi, K. Masuzaki, K. Uejima, T. Iwamoto, T. Tatsumi, K. Imai
{"title":"55nm CMOS Technology for Low Standby Power/Generic Applications Deploying the Combination of Gate Work Function Control by HfSiON and Stress-Induced Mobility Enhancement","authors":"H. Nakamura, Y. Nakahara, N. Kimizuka, T. Abe, I. Yamamoto, T. Fukase, T. Nakayama, K. Taniguchi, K. Masuzaki, K. Uejima, T. Iwamoto, T. Tatsumi, K. Imai","doi":"10.1109/VLSIT.2006.1705265","DOIUrl":"https://doi.org/10.1109/VLSIT.2006.1705265","url":null,"abstract":"A 55nm node low standby power/generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of transistor performance and process simplicity. Ion of 525/295 muA/mum at Ion of 20 muA/mum and Ion of 780/400 muA/mum at Ioff of 3 nA/mum with supply voltage of 1.2 V have been achieved. A leading-edge ArF immersion lithography has been utilized for fine-pitch design rules such as L/S of 160 nm for metal 1 layer. A 0.432 mum2 SRAM cell shows a sufficient SNM of 130 mV at supply voltage of 0.8 V","PeriodicalId":247459,"journal":{"name":"2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130082483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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