Proceedings of the 14th International Workshop on Network on Chip Architectures最新文献

A scalable NoC topology targeting network performance 针对网络性能的可扩展NoC拓扑

Proceedings of the 14th International Workshop on Network on Chip Architectures Pub Date : 2021-10-18 DOI: 10.1145/3477231.3490428

Avik Bose, P. Ghosal

引用次数: 1

Loopback strategy for in-vehicle network processing in automotive gateway network on chip 片上汽车网关网络中车载网络处理的环回策略

Proceedings of the 14th International Workshop on Network on Chip Architectures Pub Date : 2021-10-18 DOI: 10.1145/3477231.3490429

Angela Gonzalez Mariño, F. Fons, Haigang Zhang, J. M. Aróstegui

{"title":"Loopback strategy for in-vehicle network processing in automotive gateway network on chip","authors":"Angela Gonzalez Mariño, F. Fons, Haigang Zhang, J. M. Aróstegui","doi":"10.1145/3477231.3490429","DOIUrl":"https://doi.org/10.1145/3477231.3490429","url":null,"abstract":"In this work, authors introduce an innovative loopback strategy for In-Vehicle Network (IVN) processing in automotive gateway (GW) Network on Chip. The new proposed architecture is fully HW centric, and allows performing any IVN processing algorithms without intervention from the CPU. In essence, the loopback strategy allows for adapting the number of stages in the pipeline of the processing stage by betting on the centralization of the processing resources and recirculating frames from output to input when further stages are needed. It permits even to select to which stage to send them depending on the processing required, optimizing thus the number of stages traversed by frames and consequently reducing latency. The processing unit is built as a stack of parallel tasks with the required interconnection resources that allow performing any processing over any frame, and to handle several frames in parallel. With this architecture, the GW data path is fully adaptable per frame, optimizing latency and Quality of Service, allowing for fulfilling the high demanding requirements of future IVNs.","PeriodicalId":246229,"journal":{"name":"Proceedings of the 14th International Workshop on Network on Chip Architectures","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114464235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Performance analysis of application-specific instruction-set routers in networks-on-chip 片上网络中专用指令集路由器的性能分析

Proceedings of the 14th International Workshop on Network on Chip Architectures Pub Date : 2021-10-18 DOI: 10.1145/3477231.3490426

J. Rettkowski, Julian Haase, Sven Primus, M. Hübner, D. Göhringer

引用次数: 2

Dead flit attack on NoC by hardware trojan and its impact analysis 硬件木马对NoC的死飞攻击及其影响分析

Proceedings of the 14th International Workshop on Network on Chip Architectures Pub Date : 2021-10-18 DOI: 10.1145/3477231.3490425

Mohammad Humam Khan, Ruchika Gupta, John Jose, Sukumar Nandi

{"title":"Dead flit attack on NoC by hardware trojan and its impact analysis","authors":"Mohammad Humam Khan, Ruchika Gupta, John Jose, Sukumar Nandi","doi":"10.1145/3477231.3490425","DOIUrl":"https://doi.org/10.1145/3477231.3490425","url":null,"abstract":"With the advancement in VLSI technology, Tiled Chip Multicore Processors (TCMPs) with packet switched Network-on-Chip (NoC) have emerged as the most popular design choice for compute and data intensive embedded and parallel systems. Tight time-to-market constraints and budget limitations have forced the designers to explore the possibilities of using several third party Intellectual Property (IP) cores. Use of such unsecured inexpensive third party IPs may pose severe security challenges that are not detected at manufacturing and testing phases. Recent research shows that manipulation of the NoC packet content by Hardware Trojan (HT) has the potential to disrupt the on-chip communication resulting in application level stalling. We model a novel HT that alters the common prefix field of NoC packets leading to the creation of dead flits in router buffers. We introduce two variants of this proposed HT: one that modifies head flit to body flit and another one that modifies the body flit to head flit. We analyze the HT impact at core level, cache level, and NoC level. The experimental analysis on a 16-core TCMP demonstrates that the proposed HT significantly reduces IPC, increases the average cache miss penalty, and increases the average buffer occupancy of selected packets in NoC.","PeriodicalId":246229,"journal":{"name":"Proceedings of the 14th International Workshop on Network on Chip Architectures","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115956124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Machine learning for design and optimization challenges in multi/many-core network-on-chip 机器学习在多核/多核片上网络中的设计和优化挑战

Proceedings of the 14th International Workshop on Network on Chip Architectures Pub Date : 2021-10-18 DOI: 10.1145/3477231.3490427

Md Farhadur Reza

{"title":"Machine learning for design and optimization challenges in multi/many-core network-on-chip","authors":"Md Farhadur Reza","doi":"10.1145/3477231.3490427","DOIUrl":"https://doi.org/10.1145/3477231.3490427","url":null,"abstract":"Due to the advancement of transistor technology, a single chip processor can now have hundreds of cores. Network-on-Chip (NoC) has been the superior interconnect fabric for multi/many-core on-chip systems because of its scalability and parallelism. Due to the rise of dark silicon with the end of Dennard Scaling, it becomes essential to design energy-efficient, high performance, and reliable heterogeneous many-core NoC based systems. Because of the large and complex design space, multi/many-core NoC design space becomes difficult to explore for optimal trade-offs of energy-performance-reliability at both design-time and run-time. Furthermore, reactive resource management is not effective in preventing problems, such as creating thermal hotspots and exceeding power budget, from happening in adaptive system. Therefore, in this work, we explore machine learning techniques to design and configure the NoC resources in many-core systems based on the learning of the system and applications workloads. Machine learning can automatically learn from past experiences and guide the many-core system intelligently to achieve its objective on performance, power, and reliability. We have presented many-core NoC based systems design and resource management challenges, and explore and propose machine learning models to uncover near-optimal solutions quickly. Simulation results have been demonstrated to show the effectiveness of a machine learning technique.","PeriodicalId":246229,"journal":{"name":"Proceedings of the 14th International Workshop on Network on Chip Architectures","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114500845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2