Machine learning for design and optimization challenges in multi/many-core network-on-chip

Abstract

Due to the advancement of transistor technology, a single chip processor can now have hundreds of cores. Network-on-Chip (NoC) has been the superior interconnect fabric for multi/many-core on-chip systems because of its scalability and parallelism. Due to the rise of dark silicon with the end of Dennard Scaling, it becomes essential to design energy-efficient, high performance, and reliable heterogeneous many-core NoC based systems. Because of the large and complex design space, multi/many-core NoC design space becomes difficult to explore for optimal trade-offs of energy-performance-reliability at both design-time and run-time. Furthermore, reactive resource management is not effective in preventing problems, such as creating thermal hotspots and exceeding power budget, from happening in adaptive system. Therefore, in this work, we explore machine learning techniques to design and configure the NoC resources in many-core systems based on the learning of the system and applications workloads. Machine learning can automatically learn from past experiences and guide the many-core system intelligently to achieve its objective on performance, power, and reliability. We have presented many-core NoC based systems design and resource management challenges, and explore and propose machine learning models to uncover near-optimal solutions quickly. Simulation results have been demonstrated to show the effectiveness of a machine learning technique.