发布求助
文献互助 智能选刊 最新文献

[1992] Proceedings International Conference on Wafer Scale Integration最新文献

筛选
英文 中文
Critical area analysis 临界区域分析
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171820
D. Walker
{"title":"Critical area analysis","authors":"D. Walker","doi":"10.1109/ICWSI.1992.171820","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171820","url":null,"abstract":"The critical area is the region on an integrated circuit where the occurrence of a catastrophic spot defect will cause a functional circuit fault. The author describes how to efficiently compute detailed critical areas with the VLASIC Monte Carlo yield simulator. Methods for reducing the computational cost are described, along with some application examples. An SRAM cell failure caused by an extra second metal defect is analyzed as an example.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115179995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An enhanced one-step C-testable design of two-dimensional iterative logic arrays 二维迭代逻辑阵列的增强一步c测试设计
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171825
J.H. Kim, H. Sung
{"title":"An enhanced one-step C-testable design of two-dimensional iterative logic arrays","authors":"J.H. Kim, H. Sung","doi":"10.1109/ICWSI.1992.171825","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171825","url":null,"abstract":"The authors present an improved approach to one-step C-testability of orthogonal two-dimensional iterative logic arrays. This is an improvement of the approach of W. Huang and F. Lombardi (1988) and H. Elhuni et al. (1986). A group of sufficient conditions to test two-dimensional iterative logic arrays with a constant number of test vectors independent of the array size (C-testability) is stated. It is proved that the proposed approach requires a smaller number of test vectors than in previous works.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131811771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lithographic manufacturing techniques for wafer scale integration 用于晶圆规模集成的光刻制造技术
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171790
W. Flack, G. E. Flores
{"title":"Lithographic manufacturing techniques for wafer scale integration","authors":"W. Flack, G. E. Flores","doi":"10.1109/ICWSI.1992.171790","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171790","url":null,"abstract":"A methodology utilizing a mix-and-match approach of optical 1*lithography and e-beam lithography currently used at TRW for WSI (wafer scale integration) technologies is discussed. Field stitching techniques, design considerations, and macrocell grouping techniques which enhance field stitching capability and impact design rules are described for this mix and match e-beam and 1*optical stepper lithography process. A comparative cost analysis of WSI tooling costs, WSI wafer throughput, and WSI tooling requirements is presented to illustrate the tradeoffs among the various lithography systems. The proposed lithography process has been experimentally verified using test chip field stitching structures.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114993621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Efficient fault diagnosis of switches in wafer arrays 晶圆阵列开关的高效故障诊断
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171826
S. Rangarajan, D. Fussell, M. Malek
{"title":"Efficient fault diagnosis of switches in wafer arrays","authors":"S. Rangarajan, D. Fussell, M. Malek","doi":"10.1109/ICWSI.1992.171826","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171826","url":null,"abstract":"Considers an abstract model of a wafer-scale system where functional modules are connected by connections which run over wiring channels. Programmable switches are located at the junction of these wiring channels. The proposed technique is based on recursively finding progressive fault-free paths across regions of the wafer whose boundaries have been diagnosed to be fault-free. It is shown that such a technique will work with high probability and could be performed in time polynomial in the size of the array. The division of the wafer requires paths of short lengths and it is shown that these paths exist with high probability.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127211762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Applying WSI methods to emitter de-interleaving 应用WSI方法实现发射极去交织
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171815
G. Burke, C. Murphy, L. Rarick
{"title":"Applying WSI methods to emitter de-interleaving","authors":"G. Burke, C. Murphy, L. Rarick","doi":"10.1109/ICWSI.1992.171815","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171815","url":null,"abstract":"Examines the application of WSI (wafer scale integration) to a computationally intensive problem-emitter de-interleaving. In the context of an electronic battlefield, both friendly and hostile RF emitters must be identified and sorted. This formidable task is expected to require a computer power of 7 Gb/s. A reconfigurable WSI technique quilted logic array is used to map this problem onto a wafer. In this approach, an array of several hundred processors is used to solve the emitter de-interleaving problem. The form of the panels may be optimized for the particular application with processors, memory, or floating point functional units. Flexible interconnections allows varying numbers of processor panels to be applied to the signal processing functions. It is shown how the emitter de-interleaving problem can be solved using one 6-in wafer.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129068951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DFGs for synthesis of alternative architectures: Node activation synthesis 用于合成替代体系结构的DFGs:节点激活合成
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171818
A. Antola, F. Distante
{"title":"DFGs for synthesis of alternative architectures: Node activation synthesis","authors":"A. Antola, F. Distante","doi":"10.1109/ICWSI.1992.171818","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171818","url":null,"abstract":"High-level synthesis systems are becoming one of the necessary standards in digital design of complex architectures since they allow a high degree of freedom to the designers in exploring and evaluating architectural alternatives. This possibility is particularly interesting when complex VLSI/WSI (wafer scale integration) architectures are considered. Synthesis and evaluation of alternative architectures is performed, adopting the data flow graph (DFG) model. In particular, the problem of optimal scheduling of node activities and delay minimization is examined. Procedures for graph balancing and optimal delay distribution are provided. The balancing and minimization procedures proposed identify the optimal scheduling for node activation synthesis both in terms of the timing parameters proper to the graph (latency and throughput) and in terms of the amount of delay added to the arcs to grant correct synchronization.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127648213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Process characterization and yield assessment in hybrid wafer scale integration 混合晶圆规模集成工艺表征及良率评估
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171806
R. Turner, M. Robinson, H. Dearman, D. Pedder, A. Munns, M. J. Davies, E. A. Logan, I.D. Jamieson, I.M. McLaren
{"title":"Process characterization and yield assessment in hybrid wafer scale integration","authors":"R. Turner, M. Robinson, H. Dearman, D. Pedder, A. Munns, M. J. Davies, E. A. Logan, I.D. Jamieson, I.M. McLaren","doi":"10.1109/ICWSI.1992.171806","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171806","url":null,"abstract":"Functional yield in the hybrid approach to wafer scale integration (HWSI) is a product of the individual component yields in the HWSI assembly, including the contributions from the interconnection substrate and the pretested ICs mounted onto the substrate, and of the assembly processes employed to construct the HWSI circuit or module. The authors report process characterization and yield results for a high interconnection density silicon substrate technology, and for wire bonding and flip chip solder bonding chip connection technologies that are being developed to support HWSI module construction. The design of a SPARC CPU circuit module for parallel computing applications that uses this technology is also described.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121816796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fault tolerant tree using adaptive operational redundancy 使用自适应操作冗余的容错树
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171799
H. Mori, J. Kambara
{"title":"Fault tolerant tree using adaptive operational redundancy","authors":"H. Mori, J. Kambara","doi":"10.1109/ICWSI.1992.171799","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171799","url":null,"abstract":"The authors describe the architecture of fault-tolerant trees. This fault tolerant architecture is based on a majority decision of redundant operations. It shows that low-area redundancy and dynamic fault recovery are possible. This fault tolerant architecture is suitable for binary trees. Two basic types of fault tolerant architecture are presented: clustered architecture by a node-oriented approach and pipeline architecture by a branch-oriented approach.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115006925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
HASP-1002: a hybrid wafer scale associative string processor HASP-1002:混合晶圆规模关联字符串处理器
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171803
I. Jalowiecki, J. Reche, C. Habiger, R. Lea
{"title":"HASP-1002: a hybrid wafer scale associative string processor","authors":"I. Jalowiecki, J. Reche, C. Habiger, R. Lea","doi":"10.1109/ICWSI.1992.171803","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171803","url":null,"abstract":"The authors introduce and evaluate a multichip module produced in hybrid-WSI (wafer scale integration) technology embedded for real-time signal and data processing. The benefits and potential of the technologies of the HASP-1002 hybrid-WSI device are shown. The combination of improvements of the size-performance and the cost-performance trade-offs underlines the vitality of hybrid-WSI technologies, as traditionally the cost-performance trade-off worsens for size and weight sensitive applications.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123342455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High-level design of algorithm-driven architectures: The testability and diagnosability issue 算法驱动架构的高级设计:可测试性和可诊断性问题
[1992] Proceedings International Conference on Wafer Scale Integration Pub Date : 1992-01-22 DOI: 10.1109/ICWSI.1992.171819
A. Antola, M. Sami, D. Sciuto
{"title":"High-level design of algorithm-driven architectures: The testability and diagnosability issue","authors":"A. Antola, M. Sami, D. Sciuto","doi":"10.1109/ICWSI.1992.171819","DOIUrl":"https://doi.org/10.1109/ICWSI.1992.171819","url":null,"abstract":"Testability and diagnosability represent a mandatory step to be evaluated in the design of complex WSI (wafer scale integration) architectures before restructuring of the architecture to overcome defects can be performed. The authors propose a solution to such issues based on the analysis of testability and diagnosability of the data flow graph derived from the algorithm that has to be implemented. The results of this analysis can show, even at this level, potential test and diagnosis problems in the final architecture. Guidelines to the architectural mapping are given to overcome such problems in the final architecture definition. The authors also present a testing and diagnosis approach that guarantees optical functional fault coverage under the single-error assumption.<<ETX>>","PeriodicalId":229280,"journal":{"name":"[1992] Proceedings International Conference on Wafer Scale Integration","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127008618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书