Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures最新文献

A preliminary study on data allocation of on-chip dual memory banks 片上双存储器数据分配的初步研究

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-08-07 DOI: 10.1109/INTERA.2002.995844

Jeonghun Cho, Jinhwan Kim, Y. Paek

{"title":"A preliminary study on data allocation of on-chip dual memory banks","authors":"Jeonghun Cho, Jinhwan Kim, Y. Paek","doi":"10.1109/INTERA.2002.995844","DOIUrl":"https://doi.org/10.1109/INTERA.2002.995844","url":null,"abstract":"Efficient utilization of memory space is extremely important in embedded applications. Many DSP vendors provide a dual memory bank system that allows the applications to access two memory banks simultaneously. Unfortunately, we have found that existing vendor-provided compilers cannot generate highly efficient code for dual memory space because current compiler technology is unable to fully exploit this DSP hardware feature. Thus, software developers for an embedded processor have hard time developing software by hand in assembly to exploit the hardware feature efficiently. In this paper, we present a preliminary study of a memory allocation technique for dual memory space. Through there has been some work done for dual memory banks, efficient code was generated but it required so long compilation time. Although the compilation speed is relatively of less importance for embedded processors, it still should have a reasonable upper bound particularly for industry compilers due to ever increasing demands on faster time-to-market embedded software design and implementation. To achieve such reasonable compilation speed, we simplified the dual memory bank allocation problem by decoupling our code generation into five phases: register class allocation, code compaction, memory bank assignment, register assignment and memory offset assignment. The experimental results show that our generated codes perform as good as previous work, yet reducing the compilation time dramatically.","PeriodicalId":224706,"journal":{"name":"Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117353114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quantitative evaluation of the register stack engine and optimizations for future Itanium processors 对未来安腾处理器的寄存器堆栈引擎的定量评估和优化

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-02-03 DOI: 10.1109/INTERA.2002.995843

R. D. Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, P. Wang, Daniel M. Lavery, John Paul Shen

{"title":"Quantitative evaluation of the register stack engine and optimizations for future Itanium processors","authors":"R. D. Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, P. Wang, Daniel M. Lavery, John Paul Shen","doi":"10.1109/INTERA.2002.995843","DOIUrl":"https://doi.org/10.1109/INTERA.2002.995843","url":null,"abstract":"This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.","PeriodicalId":224706,"journal":{"name":"Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124331640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Code cache management schemes for dynamic optimizers 动态优化器的代码缓存管理方案

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-02-03 DOI: 10.1109/INTERA.2002.995847

K. Hazelwood, Michael D. Smith

{"title":"Code cache management schemes for dynamic optimizers","authors":"K. Hazelwood, Michael D. Smith","doi":"10.1109/INTERA.2002.995847","DOIUrl":"https://doi.org/10.1109/INTERA.2002.995847","url":null,"abstract":"A dynamic optimizer is a software-based system that performs code modifications at runtime, and several such systems have been proposed over the past several years. These systems typically perform optimization on the level of an instruction trace, and most use caching mechanisms to store recently optimized portions of code. Since the dynamic optimizers produce variable-length code traces that are modified copies of portions of the original executable, a code cache management scheme must deal with the difficult problem of caching objects that vary in size and cannot be subdivided without adding extra jump instructions. Because of these constraints, many dynamic optimizers have chosen unsophisticated schemes, such as flushing the entire cache when it becomes full. Flushing minimizes the overhead of cache management but tends to discard many useful traces. This paper evaluates several alternative cache management schemes that identify and remove only enough traces to make room for a new trace. We find that by treating the code cache as a circular buffer, we can reduce the code cache miss rate by half of that achieved by flushing. Furthermore, this approach adds very little bookkeeping overhead and avoids the problems associated with code cache fragmentation. These characteristics are extremely important in a dynamic system since more complex strategies will do more harm than good if the overhead is too high.","PeriodicalId":224706,"journal":{"name":"Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128130418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Code compression by register operand dependency 通过寄存器操作数依赖来压缩代码

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-02-03 DOI: 10.1109/INTERA.2002.995846

K. Lin, J. Shann, C. Chung

引用次数: 3

Accuracy of profile maintenance in optimizing compilers 优化编译器中配置文件维护的准确性

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-02-03 DOI: 10.1109/INTERA.2002.995840

Youfeng Wu

引用次数: 6

On the predictability of program behavior using different input data sets 关于使用不同输入数据集的程序行为的可预测性

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-02-03 DOI: 10.1109/INTERA.2002.995842

W. Hsu, Howard Chen, P. Yew, Dong-yuan Chen

{"title":"On the predictability of program behavior using different input data sets","authors":"W. Hsu, Howard Chen, P. Yew, Dong-yuan Chen","doi":"10.1109/INTERA.2002.995842","DOIUrl":"https://doi.org/10.1109/INTERA.2002.995842","url":null,"abstract":"Smaller input data sets such as the test and the train input sets are commonly used in simulation to estimate the impact of architecture/micro-architecture features on the performance of SPEC benchmarks. They are also used for profile feedback compiler optimizations. In this paper, we examine the reliability of reduced input sets for performance simulation and profile feedback optimizations. We study the high level metrics such as IPC and procedure level profiles as well as lower level measurements such as execution paths exercised by various input sets on the SPEC2000int benchmark. Our study indicates that the test input sets are not suitable to be used for simulation because they do not have an execution profile similar to the reference input runs. The train data set is better than the test data sets at maintaining similar profiles to the reference input set. However, the observed execution paths leading to cache misses are very different between using the smaller input sets and the reference input sets. For current profile based optimizations, the differences in quality of profiles may not have a significant impact on performance, as tested on the Itanium processor with an Intel compiler. However, we believe the impact of profile quality will be greater for more aggressive profile guided optimizations, such as cache prefetching.","PeriodicalId":224706,"journal":{"name":"Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures","volume":"138 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132090270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

Code size efficiency in global scheduling for ILP processors ILP处理器全局调度中的代码大小效率

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-02-03 DOI: 10.1109/INTERA.2002.995845

Huiyang Zhou, T. Conte

{"title":"Code size efficiency in global scheduling for ILP processors","authors":"Huiyang Zhou, T. Conte","doi":"10.1109/INTERA.2002.995845","DOIUrl":"https://doi.org/10.1109/INTERA.2002.995845","url":null,"abstract":"In global scheduling for ILP processors, region-enlarging optimizations, especially tail duplication, are commonly used. The code size increase due to such optimizations, however, raises serious concerns about the affected I-cache and TLB performance. In this paper, we propose a quantitative measure of the code size efficiency at compile time for any code size related optimization. Then, based on the efficiency of tail duplication, we propose the solutions to two related problems: (1) how to achieve the best performance for a given code size increase, (2) how to get the optimal code size efficiency for any program. Our study shows that code size increase has a significant but varying impact on IPC, e.g., the first 2% code size increase results in 18.5% increase in static IPC, but less than 1% when the given code size further increases from 20% to 30%. We then use this feature to define the optimal code size efficiency and to derive a simple, yet robust threshold scheme finding it. The experimental results using SPECint95 benchmarks show that this threshold scheme finds the optimal efficiency accurately. While the optimal efficiency results show an average increase of 2% in code size, the improved I-cache performance is observed and a speedup of 17% over the natural treegion results is achieved.","PeriodicalId":224706,"journal":{"name":"Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127869510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Mastering startup costs in assembler-based compiled instruction-set simulation 掌握基于汇编器的编译指令集仿真中的启动成本

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-02-03 DOI: 10.1109/INTERA.2002.995841

Ronan Amicel, F. Bodin

引用次数: 8

Dynamically scheduling VLIW instructions with dependency information 动态调度带有依赖信息的VLIW指令

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 2002-02-03 DOI: 10.1109/INTERA.2002.995839

Sunghyun Jee, K. Palaniappan

引用次数: 10

Compiling for fine-grain concurrency: planning and performing software thread integration 细粒度并发编译:规划和执行软件线程集成

Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures Pub Date : 1900-01-01 DOI: 10.1109/INTERA.2002.995838

A. Dean

{"title":"Compiling for fine-grain concurrency: planning and performing software thread integration","authors":"A. Dean","doi":"10.1109/INTERA.2002.995838","DOIUrl":"https://doi.org/10.1109/INTERA.2002.995838","url":null,"abstract":"Embedded systems require control of many concurrent real-time activities, leading to system designs which feature multiple hardware peripherals with each providing a specific, dedicated service. These peripherals increase system size, cost, weight, power and design time. Software thread integration (STI) provides low-cost thread concurrency on general-purpose processors by automatically interleaving multiple (potentially real-time) threads of control into one. This simplifies hardware to software migration (which eliminates dedicated hardware) and can help embedded system designers meet design constraints such as size, weight, power and cost. The paper introduces automated methods for planning and performing the code transformations needed for integration of functions with more sophisticated control flows than in previous work. We demonstrate the methods by using Thrint, our post pass thread-integrating compiler, to automatically integrate multiple threads for a sample real-time embedded system with fine-grain concurrency. Previous work in thread integration required users to manually integrate loops; this is now performed automatically. The sample application generates an NTSC monochrome video signal (sending out a stream of pixels to a video DAC) with STI to replace a video refresh controller IC. Using Thrint reduces integration time from days to minutes and reclaims up to 99% of the system's fine grain idle time.","PeriodicalId":224706,"journal":{"name":"Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133583956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6