Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects最新文献

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Efficient prefix cache for network processors 网络处理器的高效前缀缓存
Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects Pub Date : 2004-08-05 DOI: 10.1109/CONECT.2004.1375199
M. Akhbarizadeh, M. Nourani
{"title":"Efficient prefix cache for network processors","authors":"M. Akhbarizadeh, M. Nourani","doi":"10.1109/CONECT.2004.1375199","DOIUrl":"https://doi.org/10.1109/CONECT.2004.1375199","url":null,"abstract":"Conventional routing cache systems store destination IP addresses in their cache directory. We present a routing cache technique that stores the most recently used route prefixes, instead of IP addresses, to achieve a significantly smaller cache size. A nesting prefix is partially represented in this cache by its minimal expansions. Such expanded prefixes are obtained using an incremental technique without any modifications to the routing table. Consequently, our cache works with most of the common route lookup algorithms and efficiently maintains coherency with the routing table. Experiments show that, for a hit ratio over 0.96, our design can achieve more than 33 times reduction in cache size, compared to a conventional routing cache.","PeriodicalId":224195,"journal":{"name":"Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133481203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Performance evaluation of the Cray X1 distributed shared memory architecture Cray X1分布式共享内存架构的性能评估
Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects Pub Date : 2004-08-05 DOI: 10.1109/CONECT.2004.1375194
T. Dunigan, J. Vetter, P. Worley
{"title":"Performance evaluation of the Cray X1 distributed shared memory architecture","authors":"T. Dunigan, J. Vetter, P. Worley","doi":"10.1109/CONECT.2004.1375194","DOIUrl":"https://doi.org/10.1109/CONECT.2004.1375194","url":null,"abstract":"The Cray X1 supercomputer is a distributed shared memory vector multiprocessor, scalable to 4096 processors and up to 65 terabytes of memory. The X1's hierarchical design uses the basic building block of the multi-streaming processor (MSP), which is capable of 12.8 GF/s for 64-bit operations. The distributed shared memory (DSM) of the X1 presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of one byte per floating point operation. Our results show that this high bandwidth and low latency for remote memory accesses translates into improved application performance on important applications, such as an Eulerian gyrokinetic-Maxwell solver. Furthermore, this architecture naturally supports programming models like the Cray shmem API, Unified Parallel C (UPC), and coarray FORTRAN (CAF), and it is imperative to select the appropriate models to exploit these features as our benchmarks demonstrate.","PeriodicalId":224195,"journal":{"name":"Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129104700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Design of a system for real-time worm detection 设计了一个实时蠕虫检测系统
Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects Pub Date : 2004-08-05 DOI: 10.1109/CONECT.2004.1375207
B. Madhusudan, J. Lockwood
{"title":"Design of a system for real-time worm detection","authors":"B. Madhusudan, J. Lockwood","doi":"10.1109/CONECT.2004.1375207","DOIUrl":"https://doi.org/10.1109/CONECT.2004.1375207","url":null,"abstract":"Recent well publicized attacks have made it clear that worms constitute a threat to Internet security. Systems that secure networks against malicious code are expected to be a part of the critical Internet infrastructure in the future. Intrusion detection and prevention systems (IDPS) currently have limited use because they can filter only known worms. We present the design and implementation of a system that automatically detects new worms in real-time by monitoring traffic on a network. The system uses field programmable gate arrays (FPGAs) to scan packets for patterns of similar content. Given that a new worm hits the network and the rate of infection is high, the system is automatically able to detect an outbreak. Frequently occurring strings in packet payloads are instantly reported as likely worm signatures.","PeriodicalId":224195,"journal":{"name":"Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131693154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Configuring a load-balanced switch in hardware 配置硬件负载均衡交换机
Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects Pub Date : 2004-08-05 DOI: 10.1109/CONECT.2004.1375201
Srikanth Arekapudi, Shang-Tse Chuang, I. Keslassy, N. McKeown
{"title":"Configuring a load-balanced switch in hardware","authors":"Srikanth Arekapudi, Shang-Tse Chuang, I. Keslassy, N. McKeown","doi":"10.1109/CONECT.2004.1375201","DOIUrl":"https://doi.org/10.1109/CONECT.2004.1375201","url":null,"abstract":"The load-balanced switch architecture is a promising way to scale router capacity. We explained previously (Keslassy, I. et al., Proc. ACM SIGCOMM, 2003) how it can be used to build a 100 Tb/s router with no centralized scheduler, no memory operating faster than the line-rate, no packet mis-sequencing, a 100% throughput guarantee for all traffic patterns, and an optical switch fabric that simply spreads traffic evenly among linecards. This switch fabric uses optical MEMS switches that are reconfigured only when linecards are added and deleted, allowing the router to function when any subset of linecards is present and working. We have also introduced a configuration algorithm that can find a correct configuration of the MEMS switches in polynomial time (Keslassy et al., Proc. IEEE Infocom '04, 2004). However, we found that our algorithm takes over 50 seconds to run in software for a 100 Tb/s router. Our goal is to restore the router to operation within 50 ms of failure. We have modified our algorithm for implementation in dedicated hardware. In particular, to simplify the Ford-Fulkerson algorithm in bipartite matches, we reduce memory accesses and use bit manipulation schemes. Then, we decompose permutations using the Slepian-Duguid algorithm and reduce the configuration time with a simplified memory scheme. Our experimental results show that it is possible to achieve the 50 ms target.","PeriodicalId":224195,"journal":{"name":"Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115460716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Internet infrastructure security 互联网基础设施安全
Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects Pub Date : 1900-01-01 DOI: 10.1109/CONECT.2004.1375214
G. Manimaran
{"title":"Internet infrastructure security","authors":"G. Manimaran","doi":"10.1109/CONECT.2004.1375214","DOIUrl":"https://doi.org/10.1109/CONECT.2004.1375214","url":null,"abstract":"Summary form only given. The Internet has grown enormously over the last decade and has become ubiquitous. Most past research has focused on improving the performance and scalability of the Internet. The issue of securing the Internet has become a central issue due to a series of attacks that shut down some of the world's most high profile Web sites. Moreover, the growing concerns for cyber terrorism have made governments and researchers realize the importance of Internet security. Securing the Internet, as in any other field of computers, is based on the principle of confidentiality and integrity. This principle exists in every field, but the presence of packet sniffers, malicious routers, covert channels, eavesdroppers, denial-of-service (DoS) in the Internet makes this problem quite challenging. There has been a surge of Internet security research in the field of information assurance, which primarily focused on protecting the data using techniques such as authentication and encryption. However, information assurance assumes that the devices responsible for encrypting, forwarding and sending are trustworthy. Researchers are now questioning these assumptions, as instances have occurred where the network infrastructure (e.g., routers, servers) is compromised to the advantage of the malicious adversaries. Therefore, Internet infrastructure security is the need of the hour.","PeriodicalId":224195,"journal":{"name":"Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133307294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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