2016 International Conference on Embedded Software (EMSOFT)最新文献_第3页

Flexible support for time and costs in scenario-aware dataflow 灵活支持场景感知数据流中的时间和成本

2016 International Conference on Embedded Software (EMSOFT) Pub Date : 2016-10-01 DOI: 10.1145/2968478.2968496

A. Hartmanns, H. Hermanns, M. Bungert

引用次数: 12

Lessons learned on assumptions and scalability with time-aware instrumentation 从使用时间感知仪器的假设和可伸缩性方面获得的经验教训

2016 International Conference on Embedded Software (EMSOFT) Pub Date : 2016-10-01 DOI: 10.1145/2968478.2975584

G. M. Tchamgoue, S. Fischmeister

{"title":"Lessons learned on assumptions and scalability with time-aware instrumentation","authors":"G. M. Tchamgoue, S. Fischmeister","doi":"10.1145/2968478.2975584","DOIUrl":"https://doi.org/10.1145/2968478.2975584","url":null,"abstract":"Software instrumentation is a key technique in many stages of the development process. Instrumentation is particularly important for profiling, debugging, performance evaluation, and security analysis of real-time and embedded systems. Unfortunately, typical software-based instrumentation methods, while useful to extract high-level information from programs, concentrate on preserving only logical correctness and are thus inadequate for time-sensitive applications for which timing must also be preserved. Time-aware instrumentation is a new view on code instrumentation, one that considers extra-functional properties and specifically timing constraints of instrumented programs. Time-aware instrumentation enables instrumenting software systems while still guaranteeing their timing requirements. This paper summarizes the work on time-aware instrumentation and highlights the lessons learned on assumptions and scalability. Specifically, it shows how strict assumptions enable a strong formal model at the expense of applicability. Subsequent relaxing of assumptions then permits scaling the concept and applying it to large real-word applications with millions lines of code. We believe that these lessons may help steer other research projects in the systems area.","PeriodicalId":223619,"journal":{"name":"2016 International Conference on Embedded Software (EMSOFT)","volume":"36 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120884105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Exploring the performance of ROS2 探索ROS2的性能

2016 International Conference on Embedded Software (EMSOFT) Pub Date : 2016-10-01 DOI: 10.1145/2968478.2968502

Yuya Maruyama, S. Kato, Takuya Azumi

引用次数: 228

The design of an efficient swap mechanism for hybrid DRAM-NVM systems 混合DRAM-NVM系统的高效交换机制设计

2016 International Conference on Embedded Software (EMSOFT) Pub Date : 2016-10-01 DOI: 10.1145/2968478.2968497

Xianzhang Chen, E. Sha, Weiwen Jiang, Qingfeng Zhuge, Junxi Chen, Jiejie Qin, Yuansong Zeng

{"title":"The design of an efficient swap mechanism for hybrid DRAM-NVM systems","authors":"Xianzhang Chen, E. Sha, Weiwen Jiang, Qingfeng Zhuge, Junxi Chen, Jiejie Qin, Yuansong Zeng","doi":"10.1145/2968478.2968497","DOIUrl":"https://doi.org/10.1145/2968478.2968497","url":null,"abstract":"Non-Volatile Memory (NVM) is becoming an attractive candidate to be the swap area in embedded systems for its near-DRAM speed, low energy consumption, high density, and byte-addressability. Swapping data from DRAM out to NVM, however, can cause large performance/energy penalty and deplete the lifetime of NVM. Traditional swap mechanisms may need to be re-studied. Even through there are several swap mechanisms proposed for the hybrid DRAM-NVM systems, most of them have limited performance without considering the data access features of applications. In this paper, we analyze the data accesses features of different applications. Then, a swap mechanism, called Refinery Swap, is proposed to improve the performance of the system, reduce energy consumption, and increase the lifetime of NVM simultaneously. Refinery Swap presented two algorithms to exploit the data access features of applications and the characteristics of different kinds of memory medias. The swap operations in the system and the writes upon NVM are reduced using Refinery Swap. Extensive experiments are conducted with standard benchmarks. The experimental results show that the lifetime of NVM for the system with Refinery Swap can be 83 times that of Linux Swap. The performance of the system with Refinery Swap can be 17 times that of DR.Swap, the state-of-the-art swap mechanism for hybrid memory embedded systems. Moreover, the energy consumption of the system achieves 17 times lower.","PeriodicalId":223619,"journal":{"name":"2016 International Conference on Embedded Software (EMSOFT)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117306140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A refinement theory for timed-dataflow analysis with support for reordering 支持重新排序的时间数据流分析的细化理论

2016 International Conference on Embedded Software (EMSOFT) Pub Date : 2016-10-01 DOI: 10.1145/2968478.2968489

J. Hausmans, M. Bekooij

{"title":"A refinement theory for timed-dataflow analysis with support for reordering","authors":"J. Hausmans, M. Bekooij","doi":"10.1145/2968478.2968489","DOIUrl":"https://doi.org/10.1145/2968478.2968489","url":null,"abstract":"Real-time stream processing applications executed on embedded multiprocessor systems often have strict throughput and latency constraints. Violating these constraints is undesired and temporal analysis methods are therefore used to prevent such violations. These analysis methods use abstractions of the analyzed applications to simplify their temporal analysis. Refinement theories have enabled the creation of deterministic abstractions of stream processing applications that are executed on multiprocessor systems. Prominent examples of such abstract models are deterministic timed-dataflow models which can be efficiently analyzed because they only have one behavior. An important aspect of a stream processing application can be that it makes use of reordered data streams between tasks. An example is the bit-reversed ordered stream produced by a Fast Fourier Transform (FFT) task. However, existing abstraction/refinement theories do not support such reordering behavior or do not handle this type of behavior correctly. This is because existing refinement theories assume that the temporal behavior of applications is orthogonal to their functional behavior, whereas this orthogonality does not always hold in the case of reordered data streams. In this paper we introduce a new refinement theory in which the potential interaction between temporal and functional behavior is taken into account. The introduced theory supports reordering of data and can therefore be used to validate existing systems with such reordering. Furthermore, the theory enables showing that deterministic dataflow models that do not apply reordering can be used as valid abstractions of systems in which reordering takes place. The applicability of the refinement theory is demonstrated by creating deterministic timed-dataflow model abstractions of a Digital Video Broadcasting Terrestrial (DVB-T) application, and a communication network in which data is reordered. With these dataflow models the guaranteed throughput and buffer capacities of implementation options are compared.","PeriodicalId":223619,"journal":{"name":"2016 International Conference on Embedded Software (EMSOFT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133282725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Real-time cache management for multi-core virtualization 多核虚拟化的实时缓存管理

2016 International Conference on Embedded Software (EMSOFT) Pub Date : 2016-10-01 DOI: 10.1145/2968478.2968480

Hyoseung Kim, R. Rajkumar

{"title":"Real-time cache management for multi-core virtualization","authors":"Hyoseung Kim, R. Rajkumar","doi":"10.1145/2968478.2968480","DOIUrl":"https://doi.org/10.1145/2968478.2968480","url":null,"abstract":"Real-time virtualization techniques have been investigated with the primary goal of consolidating multiple real-time systems onto a single hardware platform while ensuring timing predictability. However, a shared last-level cache (LLC) on recent multi-core platforms can easily hamper timing predictability due to the resulting temporal interference among consolidated workloads. Since such interference caused by the LLC is highly variable and may have not even existed in legacy systems to be consolidated, it poses a significant challenge for real-time virtualization. In this paper, we propose a real-time cache management framework for multi-core virtualization. Our framework introduces two hypervisor-level techniques, vLLC and vColoring, that enable the cache allocation of individual tasks running in a virtual machine (VM), which is not achievable by the current state of the art. Our framework also provides a cache management scheme that determines cache allocation to tasks, designs VMs in a cache-aware manner, and minimizes the aggregated utilization of VMs to be consolidated. As a proof of concept, we implemented vLLC and vColoring in the KVM hypervisor running on x86 and ARM multi-core platforms. Experimental results with three different guest OSs, namely Linux/RK, vanilla Linux and MS Windows Embedded, show that our techniques can effectively control the cache allocation of tasks in VMs. Our cache management scheme yields a significant utilization benefit compared to other approaches.","PeriodicalId":223619,"journal":{"name":"2016 International Conference on Embedded Software (EMSOFT)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116699204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34