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2003 Design, Automation and Test in Europe Conference and Exhibition最新文献

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Interconnect planning with local area constrained retiming [logic IC layout] 局域约束重定时的互连规划[逻辑IC布局]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1253649
Ruibing Lu, Cheng-Kok Koh
{"title":"Interconnect planning with local area constrained retiming [logic IC layout]","authors":"Ruibing Lu, Cheng-Kok Koh","doi":"10.1109/DATE.2003.1253649","DOIUrl":"https://doi.org/10.1109/DATE.2003.1253649","url":null,"abstract":"We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and flip-flop placement problem as a local area constrained retiming problem and solve it as a series of weighted minimum area retiming problems. Our method for early interconnect planning can reduce and even avoid design iterations between physical planning and high level designs. Experimental results show that our method can reduce the number of area violations by an average of 84% in a single interconnect planning step.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"14 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reconfigurable signal processing in wireless terminals [mobile applications] 无线终端的可重构信号处理[移动应用]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1253836
J. Helmschmidt, E. Schuler, P. Rao, S. Rossi, S. Di Matteo, R. Bonitz
{"title":"Reconfigurable signal processing in wireless terminals [mobile applications]","authors":"J. Helmschmidt, E. Schuler, P. Rao, S. Rossi, S. Di Matteo, R. Bonitz","doi":"10.1109/DATE.2003.1253836","DOIUrl":"https://doi.org/10.1109/DATE.2003.1253836","url":null,"abstract":"In this paper, we show the necessity of reconfigurable hardware for data and signal processing in wireless mobile terminals. We first identify the key processing power requirements for realizing a third generation wireless mobile terminal with multi-link and multistandard capabilities. This is done on the basis of two real-world applications: a flexible mobile rake receiver for UMTS/W-CDMA and an OFDM decoder for high-speed wireless LAN protocols. We present a software-defined concept and a system implementation for the signal processing in these applications. The system is based on a DSP for control-flow oriented tasks, dedicated hardware for predefined data-flow oriented tasks and reconfigurable hardware for software-defined data-flow oriented tasks. A new coarse-grained approach is used to implement the reconfigurable hardware, which is in the form of an array of processing elements and also contains resource management mechanisms. The features and programming concepts of the reconfigurable hardware are emphasized further in the text.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127044000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On-chip stochastic communication [SoC applications] 片上随机通信[SoC应用]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1253703
T. Dumitras, R. Marculescu
{"title":"On-chip stochastic communication [SoC applications]","authors":"T. Dumitras, R. Marculescu","doi":"10.1109/DATE.2003.1253703","DOIUrl":"https://doi.org/10.1109/DATE.2003.1253703","url":null,"abstract":"As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design and verification for systems-on-chip (SoCs) are rapidly increasing due to the inefficiency of traditional CAD tools. Relaxing the requirement of 100% correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires that SoCs be designed with some system-level fault-tolerance. In this paper, we introduce a new communication paradigm for SoCs, namely stochastic communication. The newly proposed scheme not only separates communication from computation, but also provides the required built-in fault-tolerance to DSM failures, is scalable and cheap to implement. For a generic tile-based architecture, we show how a ubiquitous multimedia application (an MP3 encoder) can be implemented using stochastic communication in an efficient and robust manner. More precisely, up to 70% data upsets, 80% packet drops because of buffer overflow, and severe levels of synchronization failures can be tolerated while maintaining a low latency.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127781603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Transaction-level models for AMBA bus architecture using SystemC 2.0 [SOC applications] 使用SystemC 2.0的AMBA总线架构的事务级模型[SOC应用]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1186667
M. Caldari, M. Conti, M. Coppola, S. Curaba, L. Pieralisi, C. Turchetti
{"title":"Transaction-level models for AMBA bus architecture using SystemC 2.0 [SOC applications]","authors":"M. Caldari, M. Conti, M. Coppola, S. Curaba, L. Pieralisi, C. Turchetti","doi":"10.1109/DATE.2003.1186667","DOIUrl":"https://doi.org/10.1109/DATE.2003.1186667","url":null,"abstract":"The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level, a finite set of architecture components (memories, arithmetic units, address generators, caches, etc) communicate among each other over shared resources (buses). Until recently, modeling architectures required pin-level hardware descriptions, typically coded in RTL. Great effort is required to design and verify the models, and simulation at this level of detail is tediously slow. Transaction level modeling is the solution. Transaction level models (TLMs) effectively create an executable platform model that simulates orders of magnitude faster than a RTL model.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132391236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Profile-driven selective code compression [embedded systems] 配置文件驱动的选择性代码压缩[嵌入式系统]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1253652
Yuan Xie, W. Wolf, H. Lekatsas
{"title":"Profile-driven selective code compression [embedded systems]","authors":"Yuan Xie, W. Wolf, H. Lekatsas","doi":"10.1109/DATE.2003.1253652","DOIUrl":"https://doi.org/10.1109/DATE.2003.1253652","url":null,"abstract":"In embedded system design, memory is one of the most restricted resources. Code compression has been proposed as a solution to reduce the code size of applications for embedded systems. Data compression techniques are used to compress programs to reduce memory size. Most previous work compresses all instructions found in an executable, without taking into account the program execution profile. In this paper, a profile-driven code compression design methodology is proposed. Program profiling information can be used to help code compression to selectively compress non-critical instructions, such that the system performance degradation due to the decompression penalty is reduced.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124425942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Estimation of bus performance for a tuplespace in an embedded architecture [factory automation application] 嵌入式体系结构中元空间的总线性能评估[工厂自动化应用]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1186693
N. Drago, F. Fummi, M. Monguzzi, G. Perbellini, M. Poncino
{"title":"Estimation of bus performance for a tuplespace in an embedded architecture [factory automation application]","authors":"N. Drago, F. Fummi, M. Monguzzi, G. Perbellini, M. Poncino","doi":"10.1109/DATE.2003.1186693","DOIUrl":"https://doi.org/10.1109/DATE.2003.1186693","url":null,"abstract":"This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristics of typical embedded architectures for factory automation. We describe the features of a bus for embedded applications and the problem of estimating its performance, and present a rapid prototyping design methodology developed for a qualitative and quantitative estimation. The methodology is based on a mix of different modeling languages such as Java, C++, SystemC and Network Simulator2 (NS2). Its application allows the estimation of the expected performance of the bus under design in relation to the developed tuplespace.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116678131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Generalized posynomial performance modeling [analog ICs] 广义多项式性能建模[模拟集成电路]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1186394
T. Eeckelaert, W. Daems, G. Gielen, W. Sansen
{"title":"Generalized posynomial performance modeling [analog ICs]","authors":"T. Eeckelaert, W. Daems, G. Gielen, W. Sansen","doi":"10.1109/DATE.2003.1186394","DOIUrl":"https://doi.org/10.1109/DATE.2003.1186394","url":null,"abstract":"This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set as well as the exponent set of the posynomial expression are determined based on SPICE simulation data with device-level accuracy. We prove that this problem corresponds to solving a non-convex optimization problem without local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows the automatic generation of an accurate sizing model that composes a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming nature of hand-crafted analytic model generation. Experimental results illustrate the capabilities and effectiveness of the presented modeling technique.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123760854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hardware/software partitioning of operating systems [SoC applications] 操作系统的硬件/软件分区[SoC应用]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1253630
V. Mooney
{"title":"Hardware/software partitioning of operating systems [SoC applications]","authors":"V. Mooney","doi":"10.1109/DATE.2003.1253630","DOIUrl":"https://doi.org/10.1109/DATE.2003.1253630","url":null,"abstract":"We present a hardware/software RTOS (real-time operating systems) generation framework for system-on-a-chip (SoC) applications. We claim that current SoC designs tend to ignore the RTOS until late in the SoC design phase. In contrast, we propose RTOS/SoC codesign where both the multiprocessor SoC architecture and a custom RTOS (with part potentially in hardware) are designed together. Thus, this paper introduces a hardware/software RTOS generation framework for customized design of an RTOS within specific predefined RTOS services and capabilities available in software and/or hardware (depending on the service or capability).","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124025693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A technique for high ratio LZW compression [logic test vector compression] 一种高比率LZW压缩技术[逻辑测试矢量压缩]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1253596
M. Knieser, F. Wolff, C. Papachristou, D. Weyer, D. R. McIntyre
{"title":"A technique for high ratio LZW compression [logic test vector compression]","authors":"M. Knieser, F. Wolff, C. Papachristou, D. Weyer, D. R. McIntyre","doi":"10.1109/DATE.2003.1253596","DOIUrl":"https://doi.org/10.1109/DATE.2003.1253596","url":null,"abstract":"Reduction of both the test suite size and the download time of test vectors is important in today's system-on-a-chip designs. In this paper, a method for compressing the scan test patterns using the LZW algorithm is presented. This method leverages the large number of \"don't-cares\" in test vectors in order to improve the compression ratio significantly. The hardware decompression architecture presented here uses existing on-chip embedded memories. Tests using the ISCAS89 and the ITC99 benchmarks show that this method achieves high compression ratios.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126486991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Masking the energy behavior of DES encryption [smart cards] 屏蔽DES加密的能量行为[智能卡]
2003 Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2003-12-19 DOI: 10.1109/DATE.2003.1253591
H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, Soontae Kim, Wei Zhang
{"title":"Masking the energy behavior of DES encryption [smart cards]","authors":"H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, Soontae Kim, Wei Zhang","doi":"10.1109/DATE.2003.1253591","DOIUrl":"https://doi.org/10.1109/DATE.2003.1253591","url":null,"abstract":"Smart cards are vulnerable to both invasive and non-invasive attacks. Specifically, non-invasive attacks using power and timing measurements to extract the cryptographic key has drawn a lot of negative publicity for smart card usage. The power measurement techniques rely on the data-dependent energy behavior of the underlying system. Further, power analysis can be used to identify the specific portions of the program being executed to induce timing glitches that may in turn help to bypass key checking. Thus, it is important to mask the energy consumption when executing the encryption algorithms. In this work, we augment the instruction set architecture of a simple five-stage pipelined smart card processor with secure instructions to mask the energy differences due to key-related data-dependent computations in DES encryption. The secure versions operate on the normal and complementary versions of the operands simultaneously to mask the energy variations due to value dependent operations. However, this incurs the penalty of increased overall energy consumption in the data-path components. Consequently, we employ secure versions of instructions only for critical operations; that is we use secure instructions selectively, as directed by an optimizing compiler. Using a cycle-accurate energy simulator, we demonstrate the effectiveness of this enhancement. Our approach achieves the energy masking of critical operations consuming 83% less energy as compared to existing approaches employing dual rail circuits.","PeriodicalId":217404,"journal":{"name":"2003 Design, Automation and Test in Europe Conference and Exhibition","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128820247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
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