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1994 International Conference on Parallel Processing Vol. 1最新文献

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Partitioning of Variables for Multiple-Register-File VLIW Architectures 多寄存器文件VLIW体系结构的变量分区
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.50
Andrea Capitanio, N. Dutt, Alexandru Nicolau
{"title":"Partitioning of Variables for Multiple-Register-File VLIW Architectures","authors":"Andrea Capitanio, N. Dutt, Alexandru Nicolau","doi":"10.1109/ICPP.1994.50","DOIUrl":"https://doi.org/10.1109/ICPP.1994.50","url":null,"abstract":"Recent trends in microprocessor design heavily rely on large register files with large I/O bandwidths for sustaining performance; a possible solution to relieve this bottleneck is the adoption of multiple register files. In this paper we show how the problem of assigning variables to multiple register banks can be reduced to that of a hypergraph coloring and, also, propose a technique to perform this coloring; this technique is applied to the problem of variable partitioning for rnultipltregister- file VLIW architectures.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123448579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Deadlock-free Asynchronous Communication Strategies for Unstructured Computations on iPSC/860 iPSC/860上非结构化计算的无死锁异步通信策略
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.83
Sesh Venugopal, V. Naik
{"title":"Deadlock-free Asynchronous Communication Strategies for Unstructured Computations on iPSC/860","authors":"Sesh Venugopal, V. Naik","doi":"10.1109/ICPP.1994.83","DOIUrl":"https://doi.org/10.1109/ICPP.1994.83","url":null,"abstract":"In this paper, we describe efficient, scalable, and deadlock-free asynchronous communication strategies suitable for unstructured computations on iPSC/860. Using these deadlock-free strategies, which incur small overhead, we have optimized the communication in parallel sparse Cholesky factorization. We present experimental results to show that such optimizations can lead to more than 50% saving in communication costs.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115248939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Theory of Generalized Branch and Combine Clock Networks 广义分支与组合时钟网络理论
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.190
A. El-Amawy, P. Kulasinghe
{"title":"Theory of Generalized Branch and Combine Clock Networks","authors":"A. El-Amawy, P. Kulasinghe","doi":"10.1109/ICPP.1994.190","DOIUrl":"https://doi.org/10.1109/ICPP.1994.190","url":null,"abstract":"In a recent development a new clock distribution scheme, called Branch-and-Combine or BaC, has been introduced. The scheme is the first to guarantee constant skew bound regardless of network size. In this paper we generalize and extend the work on BaC networks. We establish some interesting results on clocking paths, node input sequences, node inputs' relative timing, network stability, and skew bound. Furthermore, this study establishes an upper bound on maximum clocking rates for BaC networks which is about double that predicted by earlier studies.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Strategies for the Massively Parallel Simulation of Interconnection Networks 互连网络的大规模并行仿真策略
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.187
Michael Jurczyk, T. Schwederski, R. Born, H. Siegel, Seth Abraham
{"title":"Strategies for the Massively Parallel Simulation of Interconnection Networks","authors":"Michael Jurczyk, T. Schwederski, R. Born, H. Siegel, Seth Abraham","doi":"10.1109/ICPP.1994.187","DOIUrl":"https://doi.org/10.1109/ICPP.1994.187","url":null,"abstract":"Methods for enhancing multistage interconnection network simulators running on massively parallel SIMD computers are presented. Aspects of parallel simulation of interconnection networks are discussed and different strategies of mapping the architecture of the network to be simulated onto the parallel machine are studied and compared. As case studies, two strategies of mapping synchronous multistage cube networks onto the MasPar MP-1 SIMD machine are explored and their implementations are compared. The methods result in an efficient simulator which can process 10^9 data packets in 40 minutes.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125821250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Distributed Cache Coherence Protocol for Hypercube Multiprocessors 一种用于超立方体多处理器的分布式缓存一致性协议
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.22
Yeimkuan Chang, L. Bhuyan, Akhilesh Kumar
{"title":"A Distributed Cache Coherence Protocol for Hypercube Multiprocessors","authors":"Yeimkuan Chang, L. Bhuyan, Akhilesh Kumar","doi":"10.1109/ICPP.1994.22","DOIUrl":"https://doi.org/10.1109/ICPP.1994.22","url":null,"abstract":"This paper proposes a distributed directory cache coherence protocol and compares the performance of the proposed protocol with fully mapped and single linked list protocols for the hypercube multiprocessors. The directories of shared blocks are maintained as a tree structure which is motivated by the similarity of the indirect binary n-cube to the direct binary n-cube. The proposed protocol also takes advantage of the wormhole routing technique. Compared to the fully mapped and single linked list schemes, the proposed protocol reduces the memory reference latency and the network traffic.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129932480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Continuum: A Hybrid Time/Space Communications Paradigm for k-ary n-cubes 连续体:k元n-立方体的混合时间/空间通信范式
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.80
Andrew C. Flavell, Yoshizo Takahashi
{"title":"Continuum: A Hybrid Time/Space Communications Paradigm for k-ary n-cubes","authors":"Andrew C. Flavell, Yoshizo Takahashi","doi":"10.1109/ICPP.1994.80","DOIUrl":"https://doi.org/10.1109/ICPP.1994.80","url":null,"abstract":"Although major advances have been made in improving the performance of interconnection networks for parallel systems, this area continues to be an active avenue of research. This is primarily due to the important role that interconnection network performance plays in determining the overall performance of a system. In this paper we introduce the Continuum communications paradigm, which utilizes multiple, unidirectional, register-insertion buses to provide a hybrid time/space division network. A discussion of the register-insertion bus is presented, along with its extension to k-ary n-cubes. An evaluation of the Continuum paradigm by simulation is given and it is found it to provide an effective model for general inter processor communication.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Rearrangeability of Reverse Shuffle/Exchange Networks 论逆向洗牌/交换网络的可重排性
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.139
B. Park, K. Watson
{"title":"On the Rearrangeability of Reverse Shuffle/Exchange Networks","authors":"B. Park, K. Watson","doi":"10.1109/ICPP.1994.139","DOIUrl":"https://doi.org/10.1109/ICPP.1994.139","url":null,"abstract":"This paper proposes a new rearrangeable algorithm in a multistage reverse shuffle/exchange network. Currently, the best upper bound for the rearrangeability of a shuffle/exchange network in nonsymmetric networks is 3logN-3 stages. We describe the rearrangeability of reverse shuffle/exchange multistage interconnection network on every arbitrary permutation with Nleqslant16. It can be established by setting two more stages in the middle stage of the network to allow the reduced network to be topological equivalent to a class of rearrangeable networks. The results enable us to establish an upper bound, 2logN+l stages for reverse shuffle/exchange network with Nleqslant16, and leads to the possibility of this bound when Nge16.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125944350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multistage Interconnection Networks with Multiple Outlets 具有多个出口的多级互连网络
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.133
T. Hanawa, H. Amano, Yoshifumi Fujikawa
{"title":"Multistage Interconnection Networks with Multiple Outlets","authors":"T. Hanawa, H. Amano, Yoshifumi Fujikawa","doi":"10.1109/ICPP.1994.133","DOIUrl":"https://doi.org/10.1109/ICPP.1994.133","url":null,"abstract":"Multistage Interconnection Networks(MINs) with multiple outlets are networks which can support higher bandwidth than that of nonblocking networks by passing multiple packets to the same destination. A novel MIN topology with multiple outlets called Piled Banyan Switching Fabrics (PBSF) is proposed for the Simple Serial Synchronized (SSS)-MIN used in multiprocessors, and analyzed with other two types of MIN with multiple outlets called Multi-Banyan Switching Fabrics (MBSF) and Tandem Banyan Switching Fabrics (TBSF). The throughput of these MINs is evaluated and compared with both the theoretical model and simulation. The PBSF supports the best throughput and latency used for the SSS-MIN. Although the latency of the TBSF is large, the pass-through ratio is close to 1 if the number of connected banyan networks are more than 4. Therefore, the TBSF is useful for the ATM switching networks in which the relatively large latency is tolerable. The conflict-free access of these MINs is also analyzed, and it appears that rows, column, forward and backward diagonal of the matrix can be accessed without conflict.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134198965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Designing Large Hierarchical Multiprocessor Systems under Processor, Interconnection, and Packaging Advancements 在处理器、互连和封装进步下设计大型分层多处理器系统
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.88
D. Basak, D. Panda
{"title":"Designing Large Hierarchical Multiprocessor Systems under Processor, Interconnection, and Packaging Advancements","authors":"D. Basak, D. Panda","doi":"10.1109/ICPP.1994.88","DOIUrl":"https://doi.org/10.1109/ICPP.1994.88","url":null,"abstract":"A general framework for architectural design of large hierarchical multiprocessor systems under rapidly changing packaging, processor, and interconnection technologies is presented. In recent years processor boards with larger area (A) and greater pinouts are becoming feasible. Board interconnection technology has advanced from peripheral connections O(sqrt A ) to elastomeric surface connections 0(A). As processor and interconnection technology grows, there is a varying demand on the interconnection network of the system. The proposed framework is capable of taking into account all these changes in technologies and, depending on a given set of technological parameters, derive the most optimum topology. The framework is illustrated by considering the design problem of the currently popular class of k-ary n-cube cluster-c scalable architectures.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121131701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Performance and Reliability of the Multistage Bus Network 多级总线网络的性能与可靠性
1994 International Conference on Parallel Processing Vol. 1 Pub Date : 1994-08-15 DOI: 10.1109/ICPP.1994.158
L. Bhuyan, Ashwini K. Nanda, Tahsin Askar
{"title":"Performance and Reliability of the Multistage Bus Network","authors":"L. Bhuyan, Ashwini K. Nanda, Tahsin Askar","doi":"10.1109/ICPP.1994.158","DOIUrl":"https://doi.org/10.1109/ICPP.1994.158","url":null,"abstract":"A Multistage Bus Network(MBN) has been proposed as a viable alternative to the existing interconnection networks. The MBN consists of multiple stages of buses connected in a manner similar to the conventional Multistage Interconnection Networks(MINs) and has the same bandwidth at each stage. Due to the bidirectional nature of the MBN, there exist a number of separate paths between any source and destination pair. Some paths make a U-turn at an intermediate stage switch which is a common ancestor of the source and destination. We present self routing techniques for the various paths. We also present a performance analysis of a synchronous packet switched MBN and compare the results with those of a MIN. Finally we present a reliability analysis of the MBN and show its superiority over the MIN.","PeriodicalId":217179,"journal":{"name":"1994 International Conference on Parallel Processing Vol. 1","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122984641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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