28th IEEE International Real-Time Systems Symposium (RTSS 2007)最新文献

筛选
英文 中文
Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts 实现具有两级硬件中断的混合操作系统
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-03 DOI: 10.1109/RTSS.2007.10
Miao Liu, Z. Shao, M. Wang, Hongxing Wei, Tianmiao Wang
{"title":"Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts","authors":"Miao Liu, Z. Shao, M. Wang, Hongxing Wei, Tianmiao Wang","doi":"10.1109/RTSS.2007.10","DOIUrl":"https://doi.org/10.1109/RTSS.2007.10","url":null,"abstract":"In this paper, we propose to implement hybrid operating systems based on two-level hardware interrupts. To separate real-time and non-real-time hardware interrupts by hardware, we show that it is easier to build up hybrid systems with better performance. We analyze and discuss the key issues for implementing a hybrid system based on this and implement a hybrid system called RTLinux-THIN (Real-Time LINUX with Two-level Hardware Interrupts) on the ARM architecture by combining ARM Linux kernel 2.6.9 and muC/OS-II. We conduct experiments on a set of real application programs including mplayer [20], Bonnie [4] and iperf [13] and compare the interrupt latency distributions for RTLinux-THIN (with and without cache locking), RTAI and Linux on a hardware platform based on Intel PXA270processor [12]. The experimental results show that RTLinux-THIN improves real-time interrupt latencies and provides better predictability.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124784878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
ANDES: An ANalysis-Based DEsign Tool for Wireless Sensor Networks 基于分析的无线传感器网络设计工具
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-03 DOI: 10.1109/RTSS.2007.28
V. Prasad, Ting Yan, P. Jayachandran, Zengzhong Li, S. Son, J. Stankovic, J. Hansson, T. Abdelzaher
{"title":"ANDES: An ANalysis-Based DEsign Tool for Wireless Sensor Networks","authors":"V. Prasad, Ting Yan, P. Jayachandran, Zengzhong Li, S. Son, J. Stankovic, J. Hansson, T. Abdelzaher","doi":"10.1109/RTSS.2007.28","DOIUrl":"https://doi.org/10.1109/RTSS.2007.28","url":null,"abstract":"We have developed an analysis-based design tool, ANDES, for modeling a wireless sensor network system and analyzing its performance before deployment ANDES enables designers to systematically develop a model for the system, refine it iteratively by tuning the system parameters based on existing analysis techniques, and resolve key design decisions according to the required system performance. We also present a real-time communication schedulability analysis for sensor networks based on exact characterization which utilizes information regarding network topology and workload characteristics to analyze the schedulability of a set of periodic streams with real-time constraints. We further demonstrate the use of ANDES for the designers through detailed case studies where we design wireless sensor network applications (for target detection and environmental monitoring) using ANDES and validate the results through simulations. Currently, ANDES supports communication schedulability analysis, target tracking analysis and real-time capacity analysis which work on system models with differing levels of detail. ANDES has been developed by extending the AADL/OSATE framework which has been used extensively for real-time and embedded systems. Based on key insights gained from the development of this analysis tool, we address issues in AADL for its use in the field of wireless sensor networks. We have developed a plug-in for ANDES, called ModelGeneration, which bridges the gap between the semantics needed for sensor networks and the syntax supported by AADL. This makes it easy for sensor network designers to build system models that are intuitive to them. Furthermore, ANDES is extensible and new analysis techniques can be easily incorporated into the toolset.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125212080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
The Design of an EDF-Scheduled Resource-Sharing Open Environment edf调度资源共享开放环境的设计
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-03 DOI: 10.1109/RTSS.2007.23
N. Fisher, M. Bertogna, Sanjoy Baruah
{"title":"The Design of an EDF-Scheduled Resource-Sharing Open Environment","authors":"N. Fisher, M. Bertogna, Sanjoy Baruah","doi":"10.1109/RTSS.2007.23","DOIUrl":"https://doi.org/10.1109/RTSS.2007.23","url":null,"abstract":"We study the problem of executing a collection of independently designed and validated task systems upon a common platform comprised of a preemptive processor and additional shared resources. We present an abstract formulation of the problem and identify the major issues that must be addressed in order to solve this problem. We present (and prove the correctness of) algorithms that address these issues, and thereby obtain a design for an open real-time environment in the presence of shared global resources.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130067832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 81
Fast Algorithms for Testing Fault-Tolerance of Sequenced Jobs with Deadlines 带截止日期的序列作业容错测试的快速算法
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-03 DOI: 10.1109/RTSS.2007.20
M. Chrobak, M. Hurand, J. Sgall
{"title":"Fast Algorithms for Testing Fault-Tolerance of Sequenced Jobs with Deadlines","authors":"M. Chrobak, M. Hurand, J. Sgall","doi":"10.1109/RTSS.2007.20","DOIUrl":"https://doi.org/10.1109/RTSS.2007.20","url":null,"abstract":"In queue-based scheduling systems jobs are executed according to a predefined sequential plan. During execution, faults may occur that cause jobs to re-execute, thus delaying the whole schedule. It is thus important to determine (in real-time) whether the given set of pre-ordered jobs is fault-tolerant, that is, if all jobs will always meet their deadlines. This allows, for instance, to decide online whether to admit a new urgent job into the queue while still guaranteeing that the whole schedule remains fault-tolerant. Our goal in this work is to design efficient algorithm for testing fault tolerance of sequenced jobs in the presence of transient faults. We consider different fault models that specify which fault patterns are allowed to occur and how soon failed jobs can be restarted. For each fault model we provide efficient algorithms that determine the feasibility of all jobs in the schedule. Our algorithms are exact and run in time linear in the number of jobs (deterministically, or with very high probability, depending on the fault model), and thus can be used to make real-time decisions.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121820435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A UML-Based Design Framework for Time-Triggered Applications 时间触发应用的基于uml的设计框架
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-03 DOI: 10.1109/RTSS.2007.18
K. D. Nguyen, P. Thiagarajan, W. Wong
{"title":"A UML-Based Design Framework for Time-Triggered Applications","authors":"K. D. Nguyen, P. Thiagarajan, W. Wong","doi":"10.1109/RTSS.2007.18","DOIUrl":"https://doi.org/10.1109/RTSS.2007.18","url":null,"abstract":"Time-triggered architectures (TTAs) are strong candidate platforms for safety-critical real-time applications. A typical time-triggered architecture is constituted by one or more clusters. Each cluster consists of nodes communicating with one another via a time-triggered communication protocol. Designing applications to run on such a platform is a challenging task. We address this problem by constructing a UML-based design framework which exposes the essential features of the time-triggered platforms at the UML-level and allows applications to be developed at a more abstract level before full implementation. To support preliminary functional validation, we have constructed a translator by which SystemC code can be automatically generated from UML designs. Our framework enables fast prototyping of time-triggered applications and early design validation. It also supports key design principles of TTAs, such as temporal firewalls and composability.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115738461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Integrating Adaptive Components: An Emerging Challenge in Performance-Adaptive Systems and a Server Farm Case-Study 集成自适应组件:性能自适应系统中的新挑战和服务器场案例研究
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-03 DOI: 10.1109/RTSS.2007.48
Jin Heo, D. Henriksson, Xue Liu, T. Abdelzaher
{"title":"Integrating Adaptive Components: An Emerging Challenge in Performance-Adaptive Systems and a Server Farm Case-Study","authors":"Jin Heo, D. Henriksson, Xue Liu, T. Abdelzaher","doi":"10.1109/RTSS.2007.48","DOIUrl":"https://doi.org/10.1109/RTSS.2007.48","url":null,"abstract":"The increased complexity of performance-sensitive software systems leads to increased use of automated adaptation policies in lieu of manual performance tuning. Composition of adaptive components into larger adaptive systems, however, presents challenges that arise from potential incompatibilities among the respective adaptation policies. Consequently, unstable or poorly-tuned feedback loops may result that cause performance deterioration. This paper (i) presents a mechanism, called adaptation graph analysis, for identifying potential incompatibilities between composed adaptation policies and (ii) illustrates a general design methodology for co-adaptation that resolves such incompatibilities. Our results are demonstrated by a case study on energy minimization in multi-tier Web server farms subject to soft real-time constraints. Two independently efficient energy saving policies (an on/off policy that switches machines off when not needed and a dynamic voltage scaling policy) are shown to conflict leading to increased energy consumption when combined. Our adaptation graph analysis predicts the problem, and our co-adaptation design methodology finds a solution that improves performance. Experimental results from a 17-server farm running the industry standard TPC-W e-commerce benchmark show that co-adaptation renders a cut-down in energy consumption by more than 50%, when workload is not high, while maintaining latency within acceptable bounds. The paper serves as a proof of concept of the proposed conflict-identification and resolution methodology and an invitation to further investigate a science for composing adaptive systems.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132954211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 269
Analysis of Hierarchical EDF Pre-emptive Scheduling 分层EDF抢占调度分析
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-03 DOI: 10.1109/RTSS.2007.12
Fengxiang Zhang, A. Burns
{"title":"Analysis of Hierarchical EDF Pre-emptive Scheduling","authors":"Fengxiang Zhang, A. Burns","doi":"10.1109/RTSS.2007.12","DOIUrl":"https://doi.org/10.1109/RTSS.2007.12","url":null,"abstract":"This paper focuses on scheduling different hard real-time applications on a uniprocessor when the earliest deadline first algorithm is used as the local scheduler, and the global scheduler of the system could be fixed priority (FP) or earliest deadline first (EDF). Each application task could be periodic or sporadic, bound or unbound, with arbitrary relative deadline which could be less than, equal to or greater than its period. A number of different server types are considered. This paper presents an exact and efficient schedulability test for the application tasks based on the capacity demand criterion when the global scheduler could be FP or EDF, in some cases, it is necessary and sufficient. Schedulability tests which are necessary and sufficient for several types of dynamic servers are presented when the global scheduler is EDF.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121347847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 60
Verifying Linear Real-Time Logic Specifications 验证线性实时逻辑规格
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-03 DOI: 10.1109/RTSS.2007.14
S. Andrei, A. Cheng
{"title":"Verifying Linear Real-Time Logic Specifications","authors":"S. Andrei, A. Cheng","doi":"10.1109/RTSS.2007.14","DOIUrl":"https://doi.org/10.1109/RTSS.2007.14","url":null,"abstract":"Formal specification and verification are critical to the development of safe real-time and embedded systems, which have become increasingly complex. Real-time logic (RTL) has been used to describe the specification and safety assertion of real-time systems. However, the satisfiability problem for RTL, as well as other first-order logics, is undecidable. There exist already non-trivial fragments of RTL, like path RTL and extended path RTL, for which the verification can be done efficiently. The key idea used by these RTL fragments was the so-called constraint graph. The constraint graph can express dependencies between two events, but cannot describe dependencies between three or more events. This paper presents a larger class than existing fragments of RTL for which the verification problem can also be solved efficiently. Our new class is called linear real-time logic (LRTL) and includes the existing decidable RTL fragments like path RTL and extended path RTL. The LRTL class is able to express any linear timing constraint with an arbitrary number of events variables (e.g., between three or more events). The main ingredient of the LRTL class is the use of matrices instead of the constraint graph, as a more powerful data structure capable of performing the conversion from RTL to a prepositional formula. The unsatisfiability of the prepositional formula will ensure the safety and feasibility of the given real-time system. Experimental results show that the execution times for LRTL are better than the systems expressed in extended path RTL, and comparable with those expressed in path RTL.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Performance Evaluation of a Self-Maintained Memory Module 自维护内存条的性能评估
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 2007-12-01 DOI: 10.1109/RTSS.2007.30
Weixing Ji, Feng Shi, B. Qiao, Qi Zuo, Caixia Liu
{"title":"Performance Evaluation of a Self-Maintained Memory Module","authors":"Weixing Ji, Feng Shi, B. Qiao, Qi Zuo, Caixia Liu","doi":"10.1109/RTSS.2007.30","DOIUrl":"https://doi.org/10.1109/RTSS.2007.30","url":null,"abstract":"Hardware approach emerges as one of the candidate in improving the performance of dynamic memory management. This paper presents measurements of a self-maintained memory module subjected to several different workloads. This memory module supporting explicit dynamic memory management takes advantage of the high speed of a pure hardware implementation. Object allocation and deletion are strictly bounded in time. The whole heap space is divided into two semi-spaces, and a concurrent bidirectional memory compaction algorithm is exploited, so that memory compaction can be done while mutator process is running on the processor concurrently. Reported measurements demonstrate that hardware-assisted memory management is a viable alternative to traditional explicit memory management techniques. Experimental results show that more than 60% of memory traffic is saved by the proposed memory compaction scheme compared to software-only approach. Both processor delay and program execution time are greatly reduced.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133909991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Techniques for Multiprocessor Global Schedulability Analysis 多处理器全局可调度性分析技术
28th IEEE International Real-Time Systems Symposium (RTSS 2007) Pub Date : 1900-01-01 DOI: 10.1109/RTSS.2007.35
Sanjoy Baruah
{"title":"Techniques for Multiprocessor Global Schedulability Analysis","authors":"Sanjoy Baruah","doi":"10.1109/RTSS.2007.35","DOIUrl":"https://doi.org/10.1109/RTSS.2007.35","url":null,"abstract":"The scheduling of sporadic task systems upon multiprocessor platforms is considered, when inter-processor migration is permitted. It is known that current schedulability tests for such systems perform quite poorly when compared to schedulability tests for partitioned scheduling. Limitations of current tests are identified, which may be responsible for the unsatisfactory performance of these tests. A new test that overcomes some of these limitations is proposed and proved correct.","PeriodicalId":214762,"journal":{"name":"28th IEEE International Real-Time Systems Symposium (RTSS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130687414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 216
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信
小红书