2018 19th International Symposium on Quality Electronic Design (ISQED)最新文献_第2页

Double error cellular automata-based error correction with skip-mode compact syndrome coding for resilient PUF design 基于双误差元胞自动机的跳跃型紧凑综合征编码纠错弹性PUF设计

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357322

Anthony Mattar El Raachini, Hussein Alawieh, Adam Issa, Zainab Swaidan, R. Kanj, A. Chehab, M. Saghir

{"title":"Double error cellular automata-based error correction with skip-mode compact syndrome coding for resilient PUF design","authors":"Anthony Mattar El Raachini, Hussein Alawieh, Adam Issa, Zainab Swaidan, R. Kanj, A. Chehab, M. Saghir","doi":"10.1109/ISQED.2018.8357322","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357322","url":null,"abstract":"Physical Unclonable Functions (PUFs) present an attractive security primitive due to their volatile key generation capability. Subject to environmental conditions, the PUF response, however, is prone to errors which may undermine the reliability of the system when left unaddressed. An error-correction scheme is typically used alongside the PUF circuit when used for cryptographic applications. In this paper, we propose the use of Cellular-Automata Error-Correcting Codes (CAECC) due to their simplicity and regularity. An efficient implementation of (15, 7, 5) CA-ECC encoder/decoder targeting a Xilinx Zynq-7000 device is demonstrated, and the design is validated on design compiler targeting 40nm TSMC technology. We also propose a skip-mode compact syndrome coding scheme for relaxed per-block BER. CAECC is tested in conjunction with the skip-mode scheme, and the approach is verified on ring oscillator PUF data. The skip-mode scheme is found to reduce the ring oscillator overhead up to 20% and enhance the entropy up to 23% compared to no-skip schemes.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129384230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LUPIS: Latch-up based ultra efficient processing in-memory system LUPIS:基于锁存的超高效内存处理系统

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357265

Joonseop Sim, M. Imani, Woojin Choi, Yeseong Kim, T. Simunic

{"title":"LUPIS: Latch-up based ultra efficient processing in-memory system","authors":"Joonseop Sim, M. Imani, Woojin Choi, Yeseong Kim, T. Simunic","doi":"10.1109/ISQED.2018.8357265","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357265","url":null,"abstract":"Internet of Things (IoT) involves processing massive data. This poses a huge challenge in the current computing systems due to the limited memory bandwidth. Processing in-memory (PIM) is a promising candidate to minimize this bottleneck and reduce the performance gap between processor and memory latency. We propose LUPIS (Latch-Up based Processing In-memory System) for nonvolatile memory (NVM). Unlike existing PIM techniques, which mainly focus on bitwise operation based computations and involve considerable latency and area penalty, our design facilitates computations like addition and multiplication with very low latency. This makes the system faster and more efficient as compared to the state-of-the-art technologies. We evaluate LUPIS at both circuit-level and application-level. Our evaluations show that LUPIS can enhance the performance and energy efficiency by 62× and 484× respectively as compared to a recent GPGPU architecture. Compared to the state-of-the-art PIM accelerator, our design presents 12.7× and 20.9× improvement in latency and energy consumption with insignificant overhead of 21% for area increase and one cycle for latency delay.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

An automated design flow for synthesis of optimal multi-layer multi-shape PCB coils for inductive sensing applications 一个自动设计流程，用于合成最佳多层多形状的PCB线圈，用于电感传感应用

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357303

P. Chawda

{"title":"An automated design flow for synthesis of optimal multi-layer multi-shape PCB coils for inductive sensing applications","authors":"P. Chawda","doi":"10.1109/ISQED.2018.8357303","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357303","url":null,"abstract":"This paper presents an automated flow to quickly design and layout an optimal multi-layer square, hexagonal, octagonal spiral printed circuit board (PCB) coils for inductive sensing applications. The flow takes into account several constraints including via connections in the center of the coil well ahead in the calculations for minimum inner diameter in order avoid any iteration later. Step-by-step instructions on how to find the optimal solution for a given optimization criteria e.g. coil area, coil performance parameter, application performance parameters are presented including trade-off between area vs layers and area vs coil fill ratio. Next, the paper discusses the algorithm to generate the multi-layer multi-shape coil in order to layout the coil on a PCB using computer aided design tools. An online design tool is developed based on flow proposed in this paper for inductive sensing applications and results from the tool are discussed and generated PCB coil layout to five popular PCB CAD tools is presented. The online design tool has reduced the PCB coil design time to a fraction of a minute and is being actively used by hundreds of designers worldwide.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"1 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132175154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Measuring the effectiveness of ISO26262 compliant self test library 测量符合ISO26262的自测库的有效性

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357281

F. Pratas, Thomas Dedes, Andrew Webber, M. Bemanian, I. Yarom

{"title":"Measuring the effectiveness of ISO26262 compliant self test library","authors":"F. Pratas, Thomas Dedes, Andrew Webber, M. Bemanian, I. Yarom","doi":"10.1109/ISQED.2018.8357281","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357281","url":null,"abstract":"Automotive SoCs are constantly being tested for correct functional operation, even long after they have left fabrication. The testing is done at the start of operation (car ignition) and repeatedly during operation (during the drive) to check for faults. Faults can result from, but are not restricted to, a failure in a part of a semiconductor circuit such as a failed transistor, interconnect failure due to electromigration, or faults caused by soft errors (e.g., an alpha particle switching a bit in a RAM or other circuit element). While the tests can run long after the chip was taped-out, the safety definition and test plan effort is starting as early as the specification definitions. In this paper we give an introduction to functional safety concentrating on the ISO26262 standard and we touch on a couple of approaches to functional safety for an Intellectual Property (IP) part such as a microprocessor, including software self-test libraries and logic BIST. We discuss the additional effort needed for developing a design for the automotive market. Lastly, we focus on our experience of using fault grading as a method for developing a self-test library that periodically tests the circuit operation. We discuss the effect that implementation decisions have on this effort and why it is important to start with this effort early in the design process.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116570949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A wireless multifunctional monitoring system of tower body running state based on MEMS acceleration sensor 基于MEMS加速度传感器的塔体运行状态无线多功能监测系统

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357313

Linxi Dong, Haonan Wang, Gaofeng Wang, Weimin Qiu

{"title":"A wireless multifunctional monitoring system of tower body running state based on MEMS acceleration sensor","authors":"Linxi Dong, Haonan Wang, Gaofeng Wang, Weimin Qiu","doi":"10.1109/ISQED.2018.8357313","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357313","url":null,"abstract":"This paper proposes a design of wireless monitoring system of tower body running state such as tilt angle, temperature, humidity, wind speed, etc. This design adopts the structural health monitoring (SHM) techniques to monitor the state of tower, and can be applied to both the power transmission tower and the communication tower. Although the SHM has been widely applied to civil engineering and building structures subjected to various loadings, there are few applications in the running state monitoring for the power transmission and communication towers. In this study, micro-electro-mechanical system (MEMS)-based acceleration sensor is used, in which a method is employed for calculating the tilt based on the difference between the acceleration due to combination of gravity and other stresses and the acceleration due to gravity alone. The wireless system uses wireless sensor nodes to transmit the tower running state data to the monitoring server. The wireless sensor node system consists of a short-distance wireless transmission network (ZigBee 2.4GHz) and a remote telecommunication network (Global System for Mobile Communication — GSM). By so doing, the important problem about the communication distance limitation is resolved. The performance of the monitoring system is evaluated through several experiments. The experimental results indicate the wireless monitoring system can accurately monitor the tower body running state in real time.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115194185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Back-bias generator for post-fabrication threshold voltage tuning applications in 22nm FD-SOI process 用于22nm FD-SOI工艺的后置阈值电压调谐的反向偏置发生器

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357299

Arif A. Siddiqi, Navneet Jain, M. Rashed

引用次数: 3

A path to energy-efficient spiking delayed feedback reservoir computing system for brain-inspired neuromorphic processors 脑启发神经形态处理器的高能效尖峰延迟反馈水库计算系统之路径

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357307

Kangjun Bai, Yang Yi Bradley

引用次数: 6

High-level synthesis of key based obfuscated RTL datapaths 基于键的模糊RTL数据路径的高级综合

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357321

S. A. Islam, S. Katkoori

{"title":"High-level synthesis of key based obfuscated RTL datapaths","authors":"S. A. Islam, S. Katkoori","doi":"10.1109/ISQED.2018.8357321","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357321","url":null,"abstract":"Reverse engineering (RE) a register transfer level (RTL) description allows an attacker to counterfeit intellectual property (IP) as well as introduce hardware trojans. To mitigate this risk, RTL obfuscation can be employed. Most of the existing obfuscation methods are targeted at gate-level and layout-level. In this work, we propose key based RTL obfuscation scheme at an early design phase during high-level synthesis (HLS). Given a control data flow graph (CDFG), obfuscation points are identified during scheduling and obfuscation logic is inserted during the datapath generation phase. In order to keep performance overhead low, such insertion is done only on noncritical paths. We implemented the proposed obfuscation technique in an in-house HLS system and the obfuscated RTL designs were synthesized to gate-level with Synopsys Design compiler targeting 90nm CMOS technology library. Based on the experimental results on four datapath intensive benchmarks, we demonstrate that proposed approach obfuscates the design with extremely low probability of reverse engineering. For a 32-bit obfuscation key, the average area, delay, and power overheads are 2.45%, 2.65%, and 2.61% respectively, which are reasonable.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116004709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems 在记忆神经形态系统中，具有脉冲时间依赖可塑性的双记忆电阻器突触在片上学习

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357267

Sagarvarma Sayyaparaju, S. Amer, G. Rose

{"title":"A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems","authors":"Sagarvarma Sayyaparaju, S. Amer, G. Rose","doi":"10.1109/ISQED.2018.8357267","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357267","url":null,"abstract":"Memristors are nanoscale devices that have recently been proposed for use as a synapse in brain-inspired computing systems. In this paper, we present a synapse architecture that utilizes two memristors to implement a non-volatile synaptic weight that can be configured as both positive and negative. The weight of the proposed synapse has an inherent exponential-like dependence on the change in the memristance of the devices, a property that we have capitalized to implement spike-timing-dependent plasticity (STDP) for on-chip learning in spiking neural networks. We discretize the neuron's spike in time and voltage and show that learning rate can be controlled by the clock frequency used. We show that by modulating the duty cycle of the clock, we can alleviate the detrimental effects of switching rate mismatch in the devices. We also simulated a 3 × 3 crossbar structure and presented the weight updates observed therein, hence demonstrating the feasibility of a crossbar with our synapse. We evaluated the energy consumption per spike of our approach and compared it with those in literature.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126416062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A low-power configurable adder for approximate applications 用于近似应用的低功耗可配置加法器

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357311

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

引用次数: 29