1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305)最新文献_第2页

Centralized packet filtering protocols: a new class of high performance protocols for single-hop lightwave WDM networks 集中式包过滤协议:一类用于单跳光波WDM网络的新型高性能协议

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749467

G. Papadimitriou

引用次数: 0

Throughput analysis of WDM-based dual-bus local area networks 基于wdm的双总线局域网吞吐量分析

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749468

A. Kamal, H. Hassanein

引用次数: 1

Core discovery in Internet multicast routing protocol Internet组播路由协议的核心发现

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749432

A. Gulati, S. Rai

引用次数: 6

A simulation evaluation of optimistic replicated filing in mobile environments 移动环境下乐观复制归档的仿真评估

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749419

An-I Wang, P. Reiher, R. Bagrodia

引用次数: 18

Managing mobility in a wireless ATM network 管理无线ATM网络中的移动性

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749425

M. Obaidat, C. B. Ahmed, N. Boudriga

引用次数: 0

The effects of memory-access ordering on multiple-issue uniprocessor performance 内存访问顺序对多问题单处理器性能的影响

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749452

B. Grayson, L. John, C. Chase

{"title":"The effects of memory-access ordering on multiple-issue uniprocessor performance","authors":"B. Grayson, L. John, C. Chase","doi":"10.1109/PCCC.1999.749452","DOIUrl":"https://doi.org/10.1109/PCCC.1999.749452","url":null,"abstract":"We study the effect of memory access ordering policies on processor performance. Relaxed ordering policies increase available instruction-level parallelism, but such policies must be evaluated subject to their effect on memory consistency-since virtually all microprocessors are designed to be compatible with shared memory multiprocessor systems, even uniprocessor desktop computers are constrained by the rules of multiprocessor memory consistency models. We define the set of potential parallelism-restricting ordering rules found in strong memory models. We then construct a spectrum of possible memory models by progressively relaxing these restrictions. Some of our models are similar to those of existing commercial processors, other models illustrate potential alternatives. We simulate and analyze several uniprocessor benchmarks from the SPEC95 and SPLASH-2 suites using a super scalar processor simulator (Armadillo) developed at the University of Texas at Austin. This simulator models dataflow instruction execution, branch prediction, speculative execution, memory disambiguation and an aggressive memory system. Our experiments confirm the significant benefits of a weaker memory model on processor performance. Although the absolute performance varies considerably from benchmark to benchmark, the relative performance gains of relaxing specific memory ordering constraints is surprisingly similar across most of the benchmarks.","PeriodicalId":211210,"journal":{"name":"1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126287285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high-capacity, scalable video-on-demand system architecture, based on a 3-stage Clos network 基于3级Clos网络的高容量、可扩展视频点播系统架构

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749460

F. Liotopoulos

{"title":"A high-capacity, scalable video-on-demand system architecture, based on a 3-stage Clos network","authors":"F. Liotopoulos","doi":"10.1109/PCCC.1999.749460","DOIUrl":"https://doi.org/10.1109/PCCC.1999.749460","url":null,"abstract":"We present a high performance, scalable architecture for a video on demand (VoD) system, using a three stage Clos switch. Three stage Clos switching networks have been used in the past in multiprocessor interconnection networks as well as for ATM switching fabrics due to their attractive low latency and fault tolerance properties. The proposed VoD system mainly consists of such a three stage Clos switch, which scales to 1024 OC-3 inputs and 1024 OC-3 outputs, offering more than 132 Gbps of pure switching capacity. Video data is transported through the switching network using the ATM cell format and switching protocol, connection oriented network services and fast virtual circuit switching. Routing is centrally performed by means of intelligent nearly nonblocking control algorithms, developed for Clos networks, which increase the switch utilization and significantly reduce the blocking probability at call setup. The proposed architecture can manipulate up to several Terabytes of video data and simultaneously serve 22000 to 66000 out of a total of 262144 end users. Depending on the number of middle stage switches and the control algorithm used, the blocking probability at call setup can range between zero and 5e-4.","PeriodicalId":211210,"journal":{"name":"1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128039792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

On estimating protocol performance from a formal specification 从形式化规范估计协议性能

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749434

Raymond E. Miller, Z. U. Chaudry

引用次数: 0

Buffer requirements for ABR traffic using congestion control mechanism 使用拥塞控制机制的ABR流量的缓冲要求

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749446

Ezzat S. Atieh, M. Matalgah, M. Guizani

引用次数: 2

Optimisation of the performance of a rate-based congestion control system by using fuzzy controllers 用模糊控制器优化基于速率的拥塞控制系统的性能

1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305) Pub Date : 1999-02-10 DOI: 10.1109/PCCC.1999.749438

J. Harju, K. Pulakka

引用次数: 14