2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)最新文献

Adaptive mechanisms for component-based real-time systems 基于组件的实时系统的自适应机制

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231172

G. Buttazzo, L. Santinelli

{"title":"Adaptive mechanisms for component-based real-time systems","authors":"G. Buttazzo, L. Santinelli","doi":"10.1109/AHS.2015.7231172","DOIUrl":"https://doi.org/10.1109/AHS.2015.7231172","url":null,"abstract":"When a common computing platform is shared by several software activities (tasks), the interference generated by the concurrent access to computational resources introduces unpredictable delays on task execution that may jeopardize the correct behavior of the controlled system. In safety-critical systems, an effective method for limiting such an interference is resource partitioning (or resource reservation), according to which each task is assigned a fraction of the shared resource (bandwidth) and executes in isolation as it were executing alone on a system with less resources. The advantage of this approach is that the response time of each task does not depend on the execution behavior of the other activities, but only on its own computational demand and on the amount of allocated resource. However, the resulting system performance strongly depends on a correct resource allocation, that is the size of the partitions. Given the dynamic behavior of certain applications and the difficulty of predicting their resource needs, adaptive resource management is crucial for changing the allocation to the actual resource requirements when they are not correctly estimated. This paper presents an adaptive resource reservation algorithm for partitioning the processor among concurrent real-time tasks and illustrates the analysis for computing the probability of meeting the timing constraints specified on the application tasks, and evaluating the changes on system partitions.","PeriodicalId":211069,"journal":{"name":"2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124933450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Augmented reality for robots: Virtual sensing technology applied to a swarm of e-pucks 机器人的增强现实:应用于一群电子冰球的虚拟传感技术

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231154

A. Reina, M. Salvaro, G. Francesca, L. Garattoni, Carlo Pinciroli, M. Dorigo, M. Birattari

引用次数: 24

Towards a generic and adaptive System-on-Chip controller for space exploration instrumentation 面向空间探测仪器的通用自适应片上系统控制器

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231151

X. Iturbe, D. Keymeulen, P. Yiu, D. Berisford, K. Hand, R. Carlson, Emre Ozer

{"title":"Towards a generic and adaptive System-on-Chip controller for space exploration instrumentation","authors":"X. Iturbe, D. Keymeulen, P. Yiu, D. Berisford, K. Hand, R. Carlson, Emre Ozer","doi":"10.1109/AHS.2015.7231151","DOIUrl":"https://doi.org/10.1109/AHS.2015.7231151","url":null,"abstract":"This paper introduces one of the first efforts conducted at NASA's Jet Propulsion Laboratory (JPL) to develop a generic System-on-Chip (SoC) platform to control science instruments that are proposed for future NASA missions. The SoC platform is named APEX-SoC, where APEX stands for Advanced Processor for space Exploration, and is based on a hybrid Xilinx Zynq that combines an FPGA and an ARM Cortex-A9 dual-core processor on a single chip. The Zynq implements a generic and customizable on-chip infrastructure that can be reused with a variety of instruments, and it has been coupled with a set of off-chip components that are necessary to deal with the different instruments. We have taken JPL's Compositional InfraRed Imaging Spectrometer (CIRIS), which is proposed for NASA icy moons missions, as a use-case scenario to demonstrate that the entire data processing, control and interface of an instrument can be implemented on a single device using the on-chip infrastructure described in this paper. We show that the performance results achieved in this preliminary version of the instrumentation controller are sufficient to fulfil the science requirements demanded to the CIRIS instrument in future NASA missions, such as Europa.","PeriodicalId":211069,"journal":{"name":"2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122162972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays 粗粒度可重构数组上容错循环的协同设计方法

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231157

Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, B. Meyer

{"title":"A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays","authors":"Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, B. Meyer","doi":"10.1109/AHS.2015.7231157","DOIUrl":"https://doi.org/10.1109/AHS.2015.7231157","url":null,"abstract":"We present a co-design approach to establish redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) to a whole region of a processor array for a class of Coarse-Grained Reconfigurable Arrays (CGRAs). The approach is applied to applications with mixed-criticality properties and experiencing varying Soft Error Rates (SERs) due to environmental reasons, e. g., changing altitude. The core idea is to adapt the degree of fault protection for loop programs executing in parallel on a CGRA to the level of reliability required as well as SER profiles. This is realized through claiming neighbor regions of processing elements for the execution of replicated loop nests. First, at the source code level, a compiler transformation is proposed that realizes these replication schemes in two steps: (1) replicate given parallel loop program two or three times for DMR or TMR, respectively, and (2) add appropriate error handling functions (voting or comparison) in order to detect respectively correct any single errors. Then, using the opportunities of hardware/software co-design, we propose optimized implementations of the error handling functions in software as well as in hardware. Finally, experimental results are given for the analysis of reliability gains for each proposed scheme of array replication in dependence of different SERs.","PeriodicalId":211069,"journal":{"name":"2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124604202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Mapping applications on two-level configurable hardware 在两级可配置硬件上映射应用程序

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231167

Himan Khanzadi, Y. Savaria, J. David

{"title":"Mapping applications on two-level configurable hardware","authors":"Himan Khanzadi, Y. Savaria, J. David","doi":"10.1109/AHS.2015.7231167","DOIUrl":"https://doi.org/10.1109/AHS.2015.7231167","url":null,"abstract":"Implementing applications on Reconfigurable Computing Architectures (RCAs) is an important research topic because of their high potential to accelerate a wide range of functions. Nevertheless, configuring and programming RCAs is a long-standing challenge. In this paper, we propose a design methodology to map an algorithm on an FPGA preconfigured with a Coarse-Grained Reconfigurable Architecture (CGRA). At the lowest configuration level, the architecture of the CGRA is elaborated, synthesized, placed and routed by some hardware design specialist using suitable tools. At the highest level, someone who has no particular knowledge in hardware design is however able to configure the CGRA in order to map his algorithm on a mesh of parallel computing and communicating nodes. Nevertheless, for medium and large applications, where the number of nodes varies from tens to thousands, getting good mapping of applications becomes manually intractable. Founded on well known mapping and routing algorithms that we have tailored to match our context, we propose a design methodology to automate the mapping of applications on a two-level configurable adaptive hardware fabric. Preliminary experiments on Fast Fourier Transform (FFT) and matrix multiplication applications show that the proposed methodology can lead to high throughput and/or low latency within a reasonable design time.","PeriodicalId":211069,"journal":{"name":"2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124708586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA 基于FPGA的MIMO-OFDM单径延迟反馈FFT实现

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231171

Mohammed Dali, Ryan M. Gibson, A. Amira, A. Guessoum, N. Ramzan

{"title":"An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA","authors":"Mohammed Dali, Ryan M. Gibson, A. Amira, A. Guessoum, N. Ramzan","doi":"10.1109/AHS.2015.7231171","DOIUrl":"https://doi.org/10.1109/AHS.2015.7231171","url":null,"abstract":"This paper presents a Single-path Delay Feedback (SDF) architecture for implementing a Fast Fourier Transform (FFT) processor on FPGA for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing. An FPGA resource efficient and shared multiplier technique for parallel processing of two and four data streams is demonstrated and utilized for realization within the presented SDF architecture based on a radix-2 butterfly model. The presented approach allows significant utilization efficiency of FPGA hardware-based multiplier elements opposed to a relative 50% less efficiency within conventional radix-2 SDF FPGA implemented techniques. The FPGA implementation demonstrated significant FPGA space resource savings compared to conventional radix-2 SDF methods and has been evaluated with other relative hardware architecture techniques. Additionally, the presented architecture is suitable for implementing and scaling to any FFT size N in correspondence with N = 2m. Furthermore, the proposed architecture is easily controlled through binary counter control signals. The presented architectures have been designed with Xilinx System Generator, realized and evaluated on a Virtex-5 FPGA XC5VSX240T-2FF1738 device.","PeriodicalId":211069,"journal":{"name":"2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126102221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

In-flight reconfigurable FPGA-based space systems 基于fpga的飞行可重构空间系统

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231177

N. Montealegre, D. M. Codinachs, Agustin Fernández, P. Armbruster

引用次数: 30

Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy n模冗余下空间级与COTS sram FPGA的可靠性比较

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231159

R. Glein, F. Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, J. Teich, A. Heuberger

{"title":"Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy","authors":"R. Glein, F. Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, J. Teich, A. Heuberger","doi":"10.1109/AHS.2015.7231159","DOIUrl":"https://doi.org/10.1109/AHS.2015.7231159","url":null,"abstract":"In this paper, we evaluate the suitability of different SRAM-based FPGAs for harsh radiation environments (e.g., space). In particular, we compare the space-grade and radiation-hardened by design Virtex-5QV (XQR5VFX130) with the commercial off-the-shelf Kintex-7 (KC7K325T) from Xilinx. The advantages of the latter device are: 2.5 times the resources of the space-grade FPGA, faster switching times, less power consumption, and the support of modern design tools. We focus on resource consumption as well as reliability in dependence of single event upset rates for a geostationary earth orbit satellite application, the Heinrich Hertz satellite mission. For this mission, we compare different modular redundancy schemes with different voter structures for the qualification of a digital communication receiver. A major drawback of the Kintex-7 are current-step single event latchups, which are a risk for space missions. If the use of an external voter is not possible, we suggest triple modular redundancy with one single voter at the end, whereby the Virtex-5QV in this configuration is about as reliable as the Kintex-7 in an N-modular redundancy configuration with an external high-reliable voter.","PeriodicalId":211069,"journal":{"name":"2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134326903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Redundancy evaluation process of processor components for permanent fault compensation 永久故障补偿的处理器部件冗余度评估过程

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231158

T. Koal, H. Vierhaus

{"title":"Redundancy evaluation process of processor components for permanent fault compensation","authors":"T. Koal, H. Vierhaus","doi":"10.1109/AHS.2015.7231158","DOIUrl":"https://doi.org/10.1109/AHS.2015.7231158","url":null,"abstract":"This paper presents a scalable hardware architecture for permanent fault compensation in arbitrary processor components. The utilization of this architecture is independent from the fault case and is therefore suitable for fault compensation after production as well as in the field. Through the application of this architecture, based on active hardware redundancy, a gain in reliability for a specified mission time is possible, while functionality is not degraded. System modeling in this paper enables efficiency calculations for the presented architecture considering the additional hardware for redundancy and their administrative components. Therefore an efficient selection process for processor components and their amount of redundancy is possible. Consequently, the optimal amount of redundancy for an existing system and an objective in reliability to achieve can be calculated and is furthermore available early in the design process. Beyond describing structure as well as functionality of the architecture this paper shows that the integration in existing design processes with usual methods and tools is possible. The used system model, which realizes the redundancy selection process, is described as well. Finally, an application example is used to exhibit the practicability of the presented approach. The resulting efficiency and the required costs of this approach for the chosen example are discussed.","PeriodicalId":211069,"journal":{"name":"2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116129063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fault-tolerant communication in invasive networks on chip 芯片入侵网络中的容错通信

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2015-06-15 DOI: 10.1109/AHS.2015.7231156

Jan Heisswolf, A. Weichslgartner, A. Zaib, Stephanie Friederich, Leonard Masing, C. Stein, M. Duden, Roman Klopfer, J. Teich, Thomas Wild, A. Herkersdorf, J. Becker

引用次数: 7