Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems最新文献_第2页

Enabling high performance rack-scale optical switching through global synchronisation 通过全局同步实现高性能机架级光交换

Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems Pub Date : 2017-01-25 DOI: 10.1145/3073763.3073773

Kari A. Clark, Phillip Watt

{"title":"Enabling high performance rack-scale optical switching through global synchronisation","authors":"Kari A. Clark, Phillip Watt","doi":"10.1145/3073763.3073773","DOIUrl":"https://doi.org/10.1145/3073763.3073773","url":null,"abstract":"There is a growing need for high radix switches in data centres and high performance computing. Current computing systems are interconnected using large numbers of relatively low radix (32--48 port) switches that restrict scalability and performance, while increasing cost and management complexity. In parallel, there is a growing interest in dense rack scale computing in which a single rack can contain several thousand network nodes. To meet these demands, we recently demonstrated a flexible optical switch architecture using fast tuneable lasers and coherent receivers which scales to over 1000 ports. However, using traditional clock data recovery circuits in this or any optical packet switch results in large latency and throughput penalties due to resynchronisation on each new connection. In this talk, we will address the challenges of building a fully synchronous optical switch network, of rack-scale or greater, in which a reference clock is distributed to every node to reduce resynchronisation overhead. We will firstly present results from preliminary FPGA-based experiments demonstrating the viability of synchronising a rack scale network. We will then discuss the limitations on port count, range and bit rate which would limit the ability to build larger synchronous systems in this way.","PeriodicalId":20560,"journal":{"name":"Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"101 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2017-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85813182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Microserver + micro-switch = micro-datacenter 微服务器+微交换机=微数据中心

Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems Pub Date : 2017-01-25 DOI: 10.1145/3073763.3073772

F. Abel, A. Doering

{"title":"Microserver + micro-switch = micro-datacenter","authors":"F. Abel, A. Doering","doi":"10.1145/3073763.3073772","DOIUrl":"https://doi.org/10.1145/3073763.3073772","url":null,"abstract":"Many computational workloads from commercial and scientific fields have high demands in total throughput, and energy efficiency. For example the largest radio telescope, to be built in South Africa and Australia combines cost, performance and power targets that cannot be met by the technological development until its installation. In processor architecture a design tradeoff between cost and power efficiency against single-thread performance is observed. Hence, to achieve a high system power efficiency, large-scale parallelism has to be employed. In order to maintain wire length, and hence network delays, energy losses, and cost, the volume of compute nodes and network switches has to be reduced to a minimum âĂŞ hence the term microserver. Our DOME microserver compute card measures 130 by 7.5 by 65 mm3. The presented switch module is confined to the same area (140 by 55 mm2), yet is deeper (40mm) because of the 630-pin high-speed connector. For 64 ports of 10Gbit Ethernet (10Gbase-KR) our switch consumes about 150W maximal. In addition to the switch ASIC (Intel FM6000 series), the power converters, clock generation, configuration memory and management processor is integrated on a second PCB. The switch management (âĂIJControl PointâĂİ) is implemented in a separate compute node. In the talk options to integrate the management into the switch (same volume as now) will be discussed. Another topic covered is the cooling of the microserver, and of the switch in particular, using (warm) water in the infrastructure and heat pipes on the module.","PeriodicalId":20560,"journal":{"name":"Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"94 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2017-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79613038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling 使用边缘和网络内流量节流的片上网络低成本拥塞管理

Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems Pub Date : 2017-01-25 DOI: 10.1145/3073763.3073764

Monobrata Debnath, Dimitris Konstantinou, C. Nicopoulos, G. Dimitrakopoulos, Wei-Ming Lin, Junghee Lee

引用次数: 2

Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems 第二届新兴计算系统先进互连解决方案和技术国际研讨会论文集

Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems Pub Date : 2017-01-01 DOI: 10.1145/3073763

引用次数: 1