2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation最新文献_第3页

Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems 异构嵌入式系统多目标最优控制器综合

2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation Pub Date : 2006-07-01 DOI: 10.1109/ICSAMOS.2006.300825

L. Józwiak, D. Gawlowski, A. Slusarczyk

{"title":"Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems","authors":"L. Józwiak, D. Gawlowski, A. Slusarczyk","doi":"10.1109/ICSAMOS.2006.300825","DOIUrl":"https://doi.org/10.1109/ICSAMOS.2006.300825","url":null,"abstract":"The recent spectacular progress in modern microelectronics created a big stimulus towards development of mobile, autonomous, embedded and re-configurable systems, but also resulted in many difficult to solve issues, as power and energy crisis or increased leakage power, that are especially serious for this sort of systems. What prevents the (re-)configurable heterogeneous embedded systems from becoming one of the main practically used paradigms is mainly inadequate support of the development methodologies and EDA-tools for efficient mapping of applications and producing power, energy, and speed optimized systems. As a part of our research that aims at development of effective methods and EDA-tools for the heterogeneous (re-)configurable embedded system synthesis, we performed a comparative analysis of several representative commercial and academic synthesis methods and tools for the FPGA-targeted controller synthesis. In this paper, the automatic hardware synthesis for the heterogeneous embedded systems is considered, when focusing on the efficient multi-objective controller synthesis. In particular, a part of results and conclusions from our analysis, and effective solutions of some problems observed are discussed","PeriodicalId":204190,"journal":{"name":"2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","volume":"2022 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128059827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Profiling Driven Scenario Detection and Prediction for Multimedia Applications 多媒体应用的分析驱动场景检测和预测

2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation Pub Date : 2006-07-01 DOI: 10.1109/ICSAMOS.2006.300810

S. V. Gheorghita, T. Basten, H. Corporaal

{"title":"Profiling Driven Scenario Detection and Prediction for Multimedia Applications","authors":"S. V. Gheorghita, T. Basten, H. Corporaal","doi":"10.1109/ICSAMOS.2006.300810","DOIUrl":"https://doi.org/10.1109/ICSAMOS.2006.300810","url":null,"abstract":"Modern multimedia applications usually have real-time constraints and they are implemented using heterogeneous multiprocessor systems-on-chip. Dimensioning a system requires accurate estimations of resources needed by the applications. Overestimation leads to over-dimensioning. For a good resource estimation, all the cases in which an application can run must be considered. To avoid an explosion in the number of different cases, those that are similar with respect to required resources are combined into, so called, scenarios. This paper presents a method and a tool that can automatically detect the most important variables from an application and use them to define and dynamically predict scenarios, with respect to the necessary time budget, for soft real-time multimedia applications. The tool was tested for two multimedia applications. Using a proactive scenario-based scheduler based on the scenarios and the runtime predictor generated by our tool, the cycle budget over-estimation decreases with up to 83.50%, paying an acceptable cost of up to 1.74% in the number of missed deadlines","PeriodicalId":204190,"journal":{"name":"2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131091876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors 高性能嵌入式微处理器数据缓存漏洞表征研究

2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation Pub Date : 2006-07-01 DOI: 10.1109/ICSAMOS.2006.300803

Shuai Wang, Jie S. Hu, Sotirios G. Ziavras

{"title":"On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors","authors":"Shuai Wang, Jie S. Hu, Sotirios G. Ziavras","doi":"10.1109/ICSAMOS.2006.300803","DOIUrl":"https://doi.org/10.1109/ICSAMOS.2006.300803","url":null,"abstract":"Energetic-particle induced soft errors in on-chip cache memories have become a major challenge in designing new generation reliable microprocessors. Uniformly applying conventional protection schemes such as error correcting codes (ECC) to SRAM caches may not be practical where performance, power, and die area are highly constrained, especially for embedded systems. In this paper, we propose to analyze the lifetime behavior of the data cache to identify its temporal vulnerability. For this vulnerability analysis, we develop a new lifetime model. Based on the new lifetime model, we evaluate the effectiveness of several existing schemes in reducing the vulnerability of the data cache. Furthermore, we propose to periodically invalidate clean cache lines to reduce the probability of errors being read in by the CPU. Combined with previously proposed early writeback strategies, our schemes achieve a substantially low vulnerability in the data cache, which indicate the necessity of different protection schemes for data items during various phases in their lifetime","PeriodicalId":204190,"journal":{"name":"2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125508730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Multi-Objective Topology Optimization for Networked Embedded Systems 网络化嵌入式系统的多目标拓扑优化

2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation Pub Date : 2006-07-01 DOI: 10.1109/ICSAMOS.2006.300814

T. Streichert, C. Haubelt, J. Teich

{"title":"Multi-Objective Topology Optimization for Networked Embedded Systems","authors":"T. Streichert, C. Haubelt, J. Teich","doi":"10.1109/ICSAMOS.2006.300814","DOIUrl":"https://doi.org/10.1109/ICSAMOS.2006.300814","url":null,"abstract":"In this paper, a new methodology is presented for topology optimization of networked embedded systems as they occur in automotive and avionic systems and partially in wireless sensor networks. By introducing a model which is (1.) suitable for heterogeneous networks with different communication bandwidths, (2.) modeling of routing restrictions and (3.) flexible binding of tasks onto processors, current design issues of networked embedded systems can be investigated. On the basis of this model, the presented methodology firstly allocates the required resources which can be communication links as well as computational nodes and secondly binds the functionality onto the nodes and the data dependencies onto the links such that no routing restrictions will be violated or capacities on communication links will be exceeded. By applying evolutionary algorithms, we are able to consider multiple objectives simultaneously during the optimization process and allow for a subsequent unbiased decision making. An experimental evaluation as well as a demonstration of a case study from the field of automotive electronics shows the applicability of the presented approach","PeriodicalId":204190,"journal":{"name":"2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115971737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Throughput optimization via cache partitioning for embedded multiprocessors 通过缓存分区对嵌入式多处理器进行吞吐量优化

2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation Pub Date : 2006-07-01 DOI: 10.1109/ICSAMOS.2006.300826

A. Molnos, S. Cotofana, M. Heijligers, J. V. Eijndhoven

{"title":"Throughput optimization via cache partitioning for embedded multiprocessors","authors":"A. Molnos, S. Cotofana, M. Heijligers, J. V. Eijndhoven","doi":"10.1109/ICSAMOS.2006.300826","DOIUrl":"https://doi.org/10.1109/ICSAMOS.2006.300826","url":null,"abstract":"In embedded multiprocessors cache partitioning is a known technique to eliminate inter-task cache conflicts, so to increase predictability. On such systems, the partitioning ratio is a parameter that should be tuned to optimize performance. In this paper we propose a simulated annealing (SA) based heuristic to determine the cache partitioning ratio that maximizes an application's throughput. In its core, the SA method iterates many times over many partitioning ratios, checking the resulted throughput. Hence the throughput of the system has to be estimated very fast, so we utilize a light simulation strategy. The light simulation derives the throughput from tasks' timings gathered off-line. This is possible because in an environment where tasks don't interfere with each other, their performance figures can be used in any possible combination. An application of industrial relevance (H.264 decoder) running on a parallel homogeneous platform is used to demonstrate the proposed method. For the H.264 application 9% throughput improvement is achieved when compared to the throughput obtained using methods of partitioning for the least number of misses. This is a significant improvement as it represents 45% from the theoretical throughput improvement achievable when assuming an infinite cache","PeriodicalId":204190,"journal":{"name":"2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12