2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)最新文献

{"title":"Message from the General Chairs","authors":"F. Kordon","doi":"10.1109/RSP.2005.29","DOIUrl":"https://doi.org/10.1109/RSP.2005.29","url":null,"abstract":"elcome to the dynamic and beautiful city of Montréal, and to the IEEE International Workshop on Rapid System Prototyping, now in its 16th year. The RSP workshop has established itself as a world-class conference in which participants from academia and industry interact through formal presentations and informal discussions. As the name of the conference suggests, its aims is to discuss fast development of systems and thus focus on techniques that will produce high-quality software and hardware systems through original combinations of modeling and design techniques, testing methods, and validation principles. The particular advantage of RSP is the heterogeneity of its attendees who come from diverse backgrounds, such as CAD tools (and design automation), simulation, verification/validation, prototyping, testability/testing, and many more disciplines applied either to hardware or software systems. Participants bring their own perspectives and then contribute to enriching discussions with an interdisciplinary point of view, making the RSP conference a unique area for the exchange of ideas. In addition to the strong interaction between researchers and practitioners from industry and academia, there is also strong interaction between researchers in the areas of software and hardware, which contributes to this natural intricate evolution of computer-based hardware and software systems. The technologies involved are just as diverse with software systems, reconfigurable computing, and custom hardware, and the applications range from aerospace to telecommunications systems and from military to commercial systems. We believe that this year’s workshop will meet your expectations. The success of a workshop is based on the efforts of many people. We wish to thank the Program Chairs Peter Athanas and Bret Michael for their hard and dedicated efforts to establish an interesting and high-quality program, to Gabriela Nicolescu for her significant effort on organizational matters of the workshop, to Guy Bois for his (always boring ;-) work on the financial stuff, to Jérôme Hugues for advertising the conference all over the communities, to the program committee members and the reviewers for their enthusiasm and hard work in getting the evaluations of the papers done under hard deadlines, and, last but not least, to you, for participating in this 16th RSP Workshop. We hope that you will find this 16th IEEE International Workshop on Rapid System Prototyping interesting and rewarding, and that you will enjoy the rhythm of Montréal.","PeriodicalId":202581,"journal":{"name":"2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122150886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Using Skip Graphs for Increased NUMA Locality","authors":"Samuel Thomas, Roxana Hayne, Jonad Pulaj, H. Mendes","doi":"10.1109/SBAC-PAD49847.2020.00031","DOIUrl":"https://doi.org/10.1109/SBAC-PAD49847.2020.00031","url":null,"abstract":"High-performance simulations and parallel frameworks often rely on highly scalable, concurrent data structures for system scalability. With an increased availability of NUMA architectures, we present a technique to promote NUMA-aware data parallelism inside a concurrent data structure, bringing significant quantitative and qualitative improvements on NUMA locality, as well as reduced contention for synchronized memory accesses. Our architecture is based on a data-partitioned, concurrent skip graph indexed by thread-local sequential maps. We implemented maps and relaxed priority queues using such technique. Maps show up to 6x higher CAS locality, up to a 68.6% reduction on the number of remote CAS operations, and an increase from 88.3% to 99% on the CAS success rate compared to a control implementation (subject to the same optimizations, and implementation practices). Remote memory accesses are not only reduced in number, but the larger the NUMA distance between threads, the larger the reduction is. Relaxed priority queues implemented using our technique show similar scalability improvements, with provable reduction in contention and decrease in relaxation in one of our implementations.","PeriodicalId":202581,"journal":{"name":"2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115603963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}