2022 IEEE Real-Time Systems Symposium (RTSS)最新文献

{"title":"PolyRhythm: Adaptive Tuning of a Multi-Channel Attack Template for Timing Interference","authors":"Ao Li, M. Sudvarg, Han Liu, Zhiyuan Yu, Chris Gill, Ning Zhang, H. Liu, yu. zhiyuan","doi":"10.1109/RTSS55097.2022.00028","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00028","url":null,"abstract":"As cyber-physical systems have become increasingly complex, rising computational demand has led to the ubiquitous use of multicore processors in embedded environments. Size, Weight, Power, and Cost (SWaP-C) constraints have pushed more processes onto shared platforms, including real-time tasks with deadline requirements. To prevent temporal interference among tasks running concurrently or in parallel in such systems, many operating systems provide priority-based scheduling and enforce processor reservations based on Worst-Case Execution Time (WCET) estimates. However, shared resources (both architectural components and data structures within the operating system) provide channels through which these constraints can be broken. Prior work has demonstrated that malicious execution by one or more processes can cause significant delays, leading to potential deadline misses in victim tasks. In this paper, we introduce PolyRhythm, a three-phase attack template that combines primitives across multiple architectural and kernel-based channels: (1) it uses an offline genetic algorithm to tune attack parameters based on the target hardware and OS platform; then (2) it performs an online search for regions of the attack parameter space where contention is most likely; and finally (3) it runs the attack primitives, using online reinforcement learning to adapt to dynamic execution patterns in the victim task. On a representative platform (Raspberry Pi 3B) Poly Rhythm outperforms prior work, achieving significantly more slowdown. As we show for several hardware/software platforms, Poly Rhythm also allows us to characterize the extent to which interference can occur; this helps to inform better estimates of execution times and overheads, towards preventing deadline misses in real-time systems.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126235149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Timing Guarantee for Non-Preemptive Gang Scheduling","authors":"Seong-U Lee, Nan Guan, Jinkyu Lee","doi":"10.1109/RTSS55097.2022.00021","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00021","url":null,"abstract":"Due to its efficient and predictable utilization of modern computing units, recent studies have paid attention to gang scheduling in which all threads of a real-time task should be concurrently executed on different processors. However, the studies have been biased to preemptive gang scheduling, although non-preemptive gang scheduling (NPG) is practical for inherently non-preemptive tasks and tasks that incur large preemption overhead. In this paper, focusing on a new type of priority-inversion incurred by NPG, we design a generalized NPG framework, called NPG*, under which each task has an option to allow or disallow the situation that incurs the priority-inversion specialized for NPG. To demonstrate the effectiveness of NPG* in terms of timing guarantees, we target NPG*-FP by employing fixed-priority scheduling (FP) as a prioritization policy, and develop the first NPG*-FP schedulability test and its improved version under a given assignment of the allowance/disallowance option to each task. We then develop the optimal allowance/disallowance assignment algorithm, which finds an assignment (if exists) that makes a target task set schedulable by the proposed schedulability tests. Via simulations, we demonstrate that the assignment algorithm associated with the schedulability tests for NPG*-FP can find a number of additional schedulable task sets, each of which has not been covered by the traditional NPG framework.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131032070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mixed-Criticality Scheduling of Energy-Harvesting Systems","authors":"Kankan Wang, Qingxu Deng","doi":"10.1109/RTSS55097.2022.00044","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00044","url":null,"abstract":"Energy harvesting is a promising approach to powering real-time embedded devices which are deployed wherever it is not possible or practical to recharge. Since the stochastic nature of harvested energy makes it challenging to simultaneously guarantee both timing and energy constraints of energy-harvesting real-time systems, the worst-case performance analysis becomes more crucial when analyzing the system schedulability. In this paper, we study the performance analysis problem of energy-harvesting mixed-criticality (EHMC) systems scheduled by an energy-aware adaptation of EDF. In particular, we propose a new method that can be used to derive time demand bounds for a mixed-criticality task set, which upper-bound the total amount of time required to satisfy both the processor and energy demand of the task set in any time interval of a given size for each criticality mode. Moreover, we calculate the minimum size of the capacitor for our schedulability test to be valid. Experiment results show that our approach is significantly more powerful than previous approaches to energy harvesting mixed-criticality systems.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122692604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Theoretical Approach to Determine the Optimal Size of a Thread Pool for Real-Time Systems","authors":"Daniel Casini","doi":"10.1109/RTSS55097.2022.00016","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00016","url":null,"abstract":"Parallel workloads most commonly execute onto pools of thread, allowing to dispatch and run individual nodes (e.g., implemented as C++ functions) at the user-space level. This is relevant in industrial cyber-physical systems, cloud, and edge computing, especially in systems leveraging deep neural networks (e.g., TensorFlow), where the computations are inherently parallel. When using thread pools, it is common to implement fork-join parallelism using blocking synchronization mechanisms provided by the operating system (such as condition variables), with the side effect of temporarily reducing the number of worker threads. Consequently, the served tasks may suffer from additional delays, thus potentially harming timing guarantees if such effects are not properly considered. Prior works studied such phenomena, providing methods to guarantee the timing behavior. However, the challenges introduced by thread pools with blocking synchronization cause current analyses to incur a notable pessimism. This paper tackles the problem from a different angle, proposing solutions to determine the optimal size of a thread pool in such a way as to avoid the undesired effects that arise from blocking synchronization.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114342119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Work-in-Progress: Deadline-Constrained Multi-Resource Allocation in Edge-Cloud System","authors":"Chuanchao Gao, A. Easwaran","doi":"10.1109/RTSS55097.2022.00052","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00052","url":null,"abstract":"In an edge-cloud system, end devices can offload computation intensive tasks to servers for processing, to satisfy deadline requirements of time-critical tasks, or maintain a good quality of service. Because the system has limited bandwidth and computation resource, it can be very challenging to determine where tasks should be offloaded and processed (task mapping), and how much bandwidth and computation resource should be allocated to each task (resource allocation). In this paper, we propose a task mapping and multi-resource allocation problem with both communication and computation contentions in an edge-cloud system, which aims to maximize the total profit gained by the system while meeting the deadlines of mapped tasks. Besides, the backhaul network of the proposed edge-cloud system is modeled as a directed incomplete graph with bandwidth contention on every edge of the graph. We formulate the problem into a nonconvex Mixed-Integer Nonlinear Programming (MINLP) problem and provide a linearization method to reformulate the MINLP problem into an Integer Linear Programming (ILP) problem formulation, which can be solved with ILP solvers.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126546354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Jellyfish: Timely Inference Serving for Dynamic Edge Networks","authors":"Vinod Nigade, P. Bauszat, H. Bal, Lin Wang","doi":"10.1109/RTSS55097.2022.00032","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00032","url":null,"abstract":"While high accuracy is of paramount importance for deep learning (DL) inference, serving inference requests on time is equally critical but has not been carefully studied especially when the request has to be served over a dynamic wireless network at the edge. In this paper, we propose Jellyfish—a novel edge DL inference serving system that achieves soft guarantees on end-to-end inference latency often specified as a service-level objective (SLO). To handle the network variability, Jellyfish exploits both data and deep neural network (DNN) adaptation to conduct tradeoffs between accuracy and latency. Jellyfish features a new design that enables collective adaptation policies where the decisions for data and DNN adaptations are aligned and coordinated among multiple users with varying network conditions. We propose efficient algorithms to dynamically adapt DNNs and map users, so that we fulfill latency SLOs while maximizing the overall inference accuracy. Our experiments based on a prototype implementation and real-world WiFi and LTE network traces show that Jellyfish can meet latency SLOs at around the 99th percentile while maintaining high accuracy.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132734206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exact Response-Time Bounds of Periodic DAG Tasks under Server-Based Global Scheduling","authors":"Shareef Ahmed, James H. Anderson","doi":"10.1109/RTSS55097.2022.00045","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00045","url":null,"abstract":"Artificial-intelligence (AI) techniques are revolutionizing modern safety-critical real-time systems by enabling autonomous features never seen before. However, AI-based workloads are typically expressed as processing graphs that are subject to complex tradeoffs involving parallelism and dataflow dependencies. Due to such complexities, exact analysis of graph-based tasks is challenging under most (if not all) schedulers. This paper presents a periodic server-based scheduling policy for periodic graph-based task systems and provides an exact response-time analysis under this policy. This analysis entails pseudo-polynomial time complexity for pseudo-harmonic periodic graph-based tasks, which are commonly used in practice.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114395571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Work-in-Progress: Control Skipping Sequence Synthesis to Counter Schedule-based Attacks","authors":"Sunandan Adhikary, Ipsita Koley, Srijeeta Maity, Soumyajit Dey","doi":"10.1109/RTSS55097.2022.00049","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00049","url":null,"abstract":"We present an ongoing work on countermeasure design against timing attacks specific to real-time safety-critical Cyber Physical Systems (CPS). Such attacks use timing side channels exposed due to worst-case response time based deterministic scheduling decisions. We propose a methodology to partially nullify this determinism by skipping certain control task executions and related data transmissions. As a proof of concept, we demonstrate how such strategic randomization makes it difficult to launch stealthy timing attacks on controller area network (CAN) based systems.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122539800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Latency-driven Optimization of Switching Pipeline Design in Network Chips","authors":"Jiale Chen, Xiaoqiang Wu, Debayan Roy, Hui Chen, Ping Xiang, Wenzhuo Zhang, Yuhong Feng, Wanli Chang","doi":"10.1109/RTSS55097.2022.00037","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00037","url":null,"abstract":"A network switch implements multiple services and each service is formed by a number of match-action operations through several pipeline stages. These services running in the switch equipment are to process various packets based on standard internet protocols to decide the route of each packet. Data packets come in serial to a port, where each packet is processed by a service according to the contents of the packet headers and then send out via another port. Design of the switch, i.e., mapping services to physical resources in the pipeline stages, aims to achieve low switching latency with small chip area while respecting data-flow dependencies and hardware constraints. The current practice relies on expertise of engineers empirically, which is laborious and generates mediocre results. In this paper, we propose a switching pipeline design optimizatton technique, called SPOT. Our main contributions are as follows: (i) We first formulate the bi-objective (latency and chip area) constrained design optimization problem; (ii) SPOT quickly spots a feasible solution from a largely unfeasible design space using a dependency-aware greedy algorithm; (iii) Based on the above feasible seed, SPOT explores the design space with hundreds of decision dimensions towards Pareto optimal solutions using non-dominated sorting genetic algorithm II (NSGA-II) and multi-objective tabu search (MOTS), both adapted to be deployed in this problem setting. We apply SPOT on three sets of real-world network services. In comparison to the design sheets prepared by expert engineers, experiments show that SPOT offers 20.63% shorter service latency and 4.55% smaller chip area on average. As a by-product, the power consumption is lowered by 23.72% on average, which is correlated to the chip area. For hard real-time scenarios, the longest service latency a data packet may experience is the major concern. SPOT reduces the worst-case service latency by 12.65% on average. SPOT is the first automated optimization solution for switching pipeline design in network chips, being utilized in millions of network products of various kinds and saving manual efforts from days to minutes.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115636777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"From Intuition to Coq: A Case Study in Verified Response-Time Analysis 1 of FIFO Scheduling","authors":"Kimaya Bedarkar, Mariam Vardishvili, S. Bozhko, Marco Maida, Björn B. Brandenburg","doi":"10.1109/RTSS55097.2022.00026","DOIUrl":"https://doi.org/10.1109/RTSS55097.2022.00026","url":null,"abstract":"Response-time analysis (RTA) is a key technique for the analysis of (not only) safety-critical real-time systems. It is hence crucial for published RTAs to be safe (i.e., correct), but historically this has not always been the case. To ensure the trustworthiness of RTAs, recent work has pioneered the use of formal verification. The Prosa open-source project, in particular, relies on the Coq proof assistant to mechanically check all proofs. While highly effective at eradicating human error, such formalization and automatic validation of mathematical reasoning still faces barriers to more widespread adoption as most researchers active today are not yet accustomed to the use of proof assistants. To make this approach more broadly accessible, this paper presents a case study in the verification of a novel RTA for sporadic tasks under FIFO scheduling using the Coq proof assistant. The RTA is derived twice, first using traditional, intuition-based reasoning, and once more formally in a style that highlights the similarity to the intuitive argument. The verified RTA is of interest in itself: experiments with synthetic workloads based on an automotive benchmark show the new RTA to clearly outperform a prior RTA for FIFO scheduling. The paper further explores the performance of FIFO scheduling relative to traditional fixed-priority and earliest-deadline-first approaches, showing that FIFO scheduling can benefit lower-rate tasks.","PeriodicalId":202402,"journal":{"name":"2022 IEEE Real-Time Systems Symposium (RTSS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123120284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}