IEEE International Conference on Formal Engineering Methods最新文献

Formally Verified Animation for RoboChart Using Interaction Trees 正式验证动画的机器人图表使用交互树

IEEE International Conference on Formal Engineering Methods Pub Date : 2023-03-16 DOI: 10.1007/978-3-031-17244-1_24

Kangfeng Ye, S. Foster, J. Woodcock

引用次数: 3

Trace Refinement in B and Event-B B和Event-B中的跟踪细化

IEEE International Conference on Formal Engineering Methods Pub Date : 2022-07-28 DOI: 10.48550/arXiv.2207.14043

Sebastian Stock, A. Mashkoor, M. Leuschel, Alexander Egyed

引用次数: 1

Machine-checked executable semantics of Stateflow Stateflow的机器检查的可执行语义

IEEE International Conference on Formal Engineering Methods Pub Date : 2022-07-25 DOI: 10.48550/arXiv.2207.11965

Shicheng Yi, Shuling Wang, Bohua Zhan, N. Zhan

引用次数: 0

PFMC: a parallel symbolic model checker for security protocol verification PFMC:用于安全协议验证的并行符号模型检查器

IEEE International Conference on Formal Engineering Methods Pub Date : 2022-07-20 DOI: 10.48550/arXiv.2207.09895

A. James, Alwen Tiu, Nisansala Yatapanage

{"title":"PFMC: a parallel symbolic model checker for security protocol verification","authors":"A. James, Alwen Tiu, Nisansala Yatapanage","doi":"10.48550/arXiv.2207.09895","DOIUrl":"https://doi.org/10.48550/arXiv.2207.09895","url":null,"abstract":". We present an investigation into the design and implementation of a parallel model checker for security protocol veriﬁcation that is based on a symbolic model of the adversary, where instantiations of concrete terms and messages are avoided until needed to resolve a particular assertion. We propose to build on this naturally lazy approach to parallelise this symbolic state exploration and evaluation. We utilise the concept of strategies in Haskell, which abstracts away from the low-level details of thread management and modularly adds parallel evaluation strategies (encapsulated as a monad in Haskell). We build on an existing symbolic model checker, OFMC, which is already implemented in Haskell. We show that there is a very signiﬁcant speed up of around 3-5 times improvement when moving from the original single-threaded implementation of OFMC to our multi-threaded version, for both the Dolev-Yao attacker model and more general algebraic attacker models. We identify several issues in parallelising the model checker: among oth-ers, controlling growth of memory consumption, balancing lazy vs strict evaluation, and achieving an optimal granularity of parallelism.","PeriodicalId":198480,"journal":{"name":"IEEE International Conference on Formal Engineering Methods","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131494874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On How to Not Prove Faulty Controllers Safe in Differential Dynamic Logic 微分动态逻辑中如何不证明故障控制器的安全性

IEEE International Conference on Formal Engineering Methods Pub Date : 2022-07-12 DOI: 10.48550/arXiv.2207.05854

Yuvaraj Selvaraj, Jonas Krook, Wolfgang Ahrendt, Martin Fabian

{"title":"On How to Not Prove Faulty Controllers Safe in Differential Dynamic Logic","authors":"Yuvaraj Selvaraj, Jonas Krook, Wolfgang Ahrendt, Martin Fabian","doi":"10.48550/arXiv.2207.05854","DOIUrl":"https://doi.org/10.48550/arXiv.2207.05854","url":null,"abstract":"Cyber-physical systems are often safety-critical and their correctness is crucial, as in the case of automated driving. Using formal mathematical methods is one way to guarantee correctness. Though these methods have shown their usefulness, care must be taken as modeling errors might result in proving a faulty controller safe, which is potentially catastrophic in practice. This paper deals with two such modeling errors in differential dynamic logic. Differential dynamic logic is a formal specification and verification language for hybrid systems, which are mathematical models of cyber-physical systems. The main contribution is to prove conditions that when fulfilled, these two modeling errors cannot cause a faulty controller to be proven safe. The problems are illustrated with a real world example of a safety controller for automated driving, and it is shown that the formulated conditions have the intended effect both for a faulty and a correct controller. It is also shown how the formulated conditions aid in finding a loop invariant candidate to prove properties of hybrid systems with feedback loops. The results are proven using the interactive theorem prover KeYmaera X.","PeriodicalId":198480,"journal":{"name":"IEEE International Conference on Formal Engineering Methods","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126882364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Extracting Weighted Finite Automata from Recurrent Neural Networks for Natural Languages 从自然语言递归神经网络中提取加权有限自动机

IEEE International Conference on Formal Engineering Methods Pub Date : 2022-06-27 DOI: 10.48550/arXiv.2206.14621

Zeming Wei, Xiyue Zhang, Meng Sun

{"title":"Extracting Weighted Finite Automata from Recurrent Neural Networks for Natural Languages","authors":"Zeming Wei, Xiyue Zhang, Meng Sun","doi":"10.48550/arXiv.2206.14621","DOIUrl":"https://doi.org/10.48550/arXiv.2206.14621","url":null,"abstract":"Recurrent Neural Networks (RNNs) have achieved tremendous success in sequential data processing. However, it is quite challenging to interpret and verify RNNs' behaviors directly. To this end, many efforts have been made to extract finite automata from RNNs. Existing approaches such as exact learning are effective in extracting finite-state models to characterize the state dynamics of RNNs for formal languages, but are limited in the scalability to process natural languages. Compositional approaches that are scablable to natural languages fall short in extraction precision. In this paper, we identify the transition sparsity problem that heavily impacts the extraction precision. To address this problem, we propose a transition rule extraction approach, which is scalable to natural language processing models and effective in improving extraction precision. Specifically, we propose an empirical method to complement the missing rules in the transition diagram. In addition, we further adjust the transition matrices to enhance the context-aware ability of the extracted weighted finite automaton (WFA). Finally, we propose two data augmentation tactics to track more dynamic behaviors of the target RNN. Experiments on two popular natural language datasets show that our method can extract WFA from RNN for natural language processing with better precision than existing approaches. Our code is available at https://github.com/weizeming/Extract_WFA_from_RNN_for_NL.","PeriodicalId":198480,"journal":{"name":"IEEE International Conference on Formal Engineering Methods","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126489945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

SMT-Based Model Checking of Industrial Simulink Models 基于smt的工业Simulink模型检验

IEEE International Conference on Formal Engineering Methods Pub Date : 2022-06-07 DOI: 10.48550/arXiv.2206.02992

Daisuke Ishii, Takashi Tomita, Toshiaki Aoki, The Quyen Ngo, Thi Bich Ngoc Do, Hideaki Takai

{"title":"SMT-Based Model Checking of Industrial Simulink Models","authors":"Daisuke Ishii, Takashi Tomita, Toshiaki Aoki, The Quyen Ngo, Thi Bich Ngoc Do, Hideaki Takai","doi":"10.48550/arXiv.2206.02992","DOIUrl":"https://doi.org/10.48550/arXiv.2206.02992","url":null,"abstract":". The development of embedded systems requires formal analysis of models such as those described with MATLAB/Simulink. How-ever, the increasing complexity of industrial models makes analysis dif-ﬁcult. This paper proposes a model checking method for Simulink models using SMT solvers. The proposed method aims at (1) automated, eﬃcient and comprehensible veriﬁcation of complex models, (2) numeri-cally accurate analysis of models, and (3) demonstrating the analysis of Simulink models using an SMT solver (we use Z3). It ﬁrst encodes a target model into a predicate logic formula in the domain of mathematical arithmetic and bit vectors. We explore how to encode various Simulink blocks exactly. Then, the method veriﬁes a given invariance property using the k -induction-based algorithm that extracts a subsystem involving the target block and unrolls the execution paths incrementally. In the experiment, we applied the proposed method and other tools to a set of models and properties. Our method successfully veriﬁed most of the properties including those unveriﬁed with other tools.","PeriodicalId":198480,"journal":{"name":"IEEE International Conference on Formal Engineering Methods","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123719301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Separation of concerning things: a simpler basis for defining and programming with the C/C++ memory model (extended version) 有关事物的分离:用C/ c++内存模型定义和编程的更简单的基础(扩展版本)

IEEE International Conference on Formal Engineering Methods Pub Date : 2022-04-07 DOI: 10.48550/arXiv.2204.03189

R. Colvin

{"title":"Separation of concerning things: a simpler basis for defining and programming with the C/C++ memory model (extended version)","authors":"R. Colvin","doi":"10.48550/arXiv.2204.03189","DOIUrl":"https://doi.org/10.48550/arXiv.2204.03189","url":null,"abstract":"The C/C++ memory model provides an interface and execution model for programmers of concurrent (shared-variable) code. It provides a range of mechanisms that abstract from underlying hardware memory models -- that govern how multicore architectures handle concurrent accesses to main memory -- as well as abstracting from compiler transformations. The C standard describes the memory model in terms of cross-thread relationships between events, and has been influenced by several research works that are similarly based. In this paper we provide a thread-local definition of the fundamental principles of the C memory model, which, for concise concurrent code, serves as a basis for relatively straightforward reasoning about the effects of the C ordering mechanisms. We argue that this definition is more practical from a programming perspective and is amenable to analysis by already established techniques for concurrent code. The key aspect is that the memory model definition is separate to other considerations of a rich programming language such as C, in particular, expression evaluation and optimisations, though we show how to reason about those considerations in the presence of C concurrency. A major simplification of our framework compared to the description in the C standard and related work in the literature is separating out considerations around the\"lack of multicopy atomicity\", a concept that is in any case irrelevant to developers of code for x86, Arm, RISC-V or SPARC architectures. We show how the framework is convenient for reasoning about well-structured code, and for formally addressing unintuitive behaviours such as\"out-of-thin-air\"writes.","PeriodicalId":198480,"journal":{"name":"IEEE International Conference on Formal Engineering Methods","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130881515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reasoning with failures 失败推理

IEEE International Conference on Formal Engineering Methods Pub Date : 2020-07-20 DOI: 10.1007/978-3-030-63406-3_3

H. Jahanian, Annabelle McIver

引用次数: 2

Parallel Chopped Symbolic Execution 并行截断符号执行

IEEE International Conference on Formal Engineering Methods Pub Date : 2020-03-01 DOI: 10.1007/978-3-030-63406-3_7

Shikhar Singh, S. Khurshid

引用次数: 4