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International Conference on Parallel Computing in Electrical Engineering最新文献

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Generalised Resource Model for Parallel Instruction Scheduling 并行指令调度的广义资源模型
International Conference on Parallel Computing in Electrical Engineering Pub Date : 2006-09-13 DOI: 10.1109/PARELEC.2006.40
Jan Müller
{"title":"Generalised Resource Model for Parallel Instruction Scheduling","authors":"Jan Müller","doi":"10.1109/PARELEC.2006.40","DOIUrl":"https://doi.org/10.1109/PARELEC.2006.40","url":null,"abstract":"In this paper we introduce a generalised resource model for parallel instruction scheduling. This model is used to formulate the resource constraints for periodic loop schedules, which are then rewritten employing an efficient flow graph model. The generalisation leads to a significant simplification and acceleration of the painful process of modelling new resource classes, and of incorporating specific processor features. Moreover, the model grants an accurate representation of the processor resources. We illustrate these properties at the examples of functional units and processor registers.","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Parallel Differential Evolution Algorithm A Parallel Differential Evolution Algorithm 一种并行差分进化算法
International Conference on Parallel Computing in Electrical Engineering Pub Date : 2006-09-13 DOI: 10.1109/PARELEC.2006.6
W. Kwedlo, K. Bandurski
{"title":"A Parallel Differential Evolution Algorithm A Parallel Differential Evolution Algorithm","authors":"W. Kwedlo, K. Bandurski","doi":"10.1109/PARELEC.2006.6","DOIUrl":"https://doi.org/10.1109/PARELEC.2006.6","url":null,"abstract":"In the paper the problem of using a differential evolution algorithm for feed-forward neural network training is considered. A new parallelization scheme for the computation of the fitness function is proposed. This scheme is based on data decomposition. Both the learning set and the population of the evolutionary algorithm are distributed among processors. The processors form a pipeline using the ring topology. In a single step each processor computes the local fitness of its current subpopulation while sending the previous subpopulation to the successor and receiving next sub-population from the predecessor. Thus it is possible to overlap communication and computation using non-blocking MPI routines. Our approach was applied to several classification and regression learning problems. The scalability of the algorithm was measured on a compute cluster consisting of sixteen two-processor servers connected by a fast infiniband interconnect. The results of initial experiments show that for large datasets the algorithm is capable of obtaining very good, near linear speedup","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114760933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Organic Computing-Vision and Challenge for System Design 有机计算视觉与系统设计的挑战
International Conference on Parallel Computing in Electrical Engineering Pub Date : 2004-09-07 DOI: 10.1109/PARELEC.2004.49
H. Schmeck
{"title":"Organic Computing-Vision and Challenge for System Design","authors":"H. Schmeck","doi":"10.1109/PARELEC.2004.49","DOIUrl":"https://doi.org/10.1109/PARELEC.2004.49","url":null,"abstract":"","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121331667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Communication Analysis for Network-on-Chip Design 片上网络设计中的通信分析
International Conference on Parallel Computing in Electrical Engineering Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.19
Axel Siebenborn, O. Bringmann, W. Rosenstiel
{"title":"Communication Analysis for Network-on-Chip Design","authors":"Axel Siebenborn, O. Bringmann, W. Rosenstiel","doi":"10.1109/PCEE.2004.19","DOIUrl":"https://doi.org/10.1109/PCEE.2004.19","url":null,"abstract":"In this paper we present an approach for the analysis of systems of parallel communicating processes, with regard to Network-on-Chip applications. We present a method to detect communications that synchronize the program flow of two or more processes. These synchronization points set the processes into relation and allow the determination of the global timing behavior of such a system. Using the results of our method for communication analysis, we present a new method to detect communications that might produce conflicts on shared communication resources. This information can be used to determine static routing in a packet routing network.","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134208872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A Parallel Hardware-Software System for Signal Processing Algorithms 信号处理算法的并行软硬件系统
International Conference on Parallel Computing in Electrical Engineering Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.7
Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, R. Merker, Jürgen Kelber
{"title":"A Parallel Hardware-Software System for Signal Processing Algorithms","authors":"Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, R. Merker, Jürgen Kelber","doi":"10.1109/PCEE.2004.7","DOIUrl":"https://doi.org/10.1109/PCEE.2004.7","url":null,"abstract":"This paper presents the implementation of a parallel hardware-software system for several digital signal processing algorithms. Besides the description of the developed hardware components, a main focus is set onto the software part: the implemented driver, libraries and user interfaces. One application of the hardware-software system is the reconstruction of tomographoc images, for which the interaction of the hardware and software parts is illustrated.","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122684322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Decentralized Traffic Control in Data Networks - A Methodological Overview 数据网络中分散的流量控制——方法论综述
International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115247
A. Karbowski
{"title":"Decentralized Traffic Control in Data Networks - A Methodological Overview","authors":"A. Karbowski","doi":"10.1109/PCEE.2002.1115247","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115247","url":null,"abstract":"The paper reviews current algorithms for distributed, asynchronous control of data networks. Different problem formulations are considered: from the simplest shortest-path approach, without quality of service (QoS) constraints, via total flow cost minimization for given traffic quality equations, until dynamic flow control with influencing users' transmission rates through internal prices. These different formulations are presented in a unified way and compared from the possible application areas point of view.","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115922160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mapping DSP Algorithms into FPGA 将DSP算法映射到FPGA
International Conference on Parallel Computing in Electrical Engineering Pub Date : 1900-01-01 DOI: 10.1109/PARELEC.2006.51
O. Maslennikov, A. Sergyienko
{"title":"Mapping DSP Algorithms into FPGA","authors":"O. Maslennikov, A. Sergyienko","doi":"10.1109/PARELEC.2006.51","DOIUrl":"https://doi.org/10.1109/PARELEC.2006.51","url":null,"abstract":"A method of mapping DSP algorithms into FPGA devices is considered. Algorithms are represented by synchronous data flow graphs, and are mapped into pipelined data path. The method consists of placing the algorithm graph in the multidimensional index space and mapping it into structure and event subspaces. The special limitations, which are injected to the mapping process, minimize both clock time and hardware volume including multiplexer inputs","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122829697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Parallelisation of Genetic Algorithms for Solving University Timetabling Problems 求解大学排课问题的并行化遗传算法
International Conference on Parallel Computing in Electrical Engineering Pub Date : 1900-01-01 DOI: 10.1109/PARELEC.2006.64
K. Banczyk, Tomasz Boinski, H. Krawczyk
{"title":"Parallelisation of Genetic Algorithms for Solving University Timetabling Problems","authors":"K. Banczyk, Tomasz Boinski, H. Krawczyk","doi":"10.1109/PARELEC.2006.64","DOIUrl":"https://doi.org/10.1109/PARELEC.2006.64","url":null,"abstract":"Genetic algorithms play an important role in solving many optimisation problems. The paper concentrates on the design of a parallel genetic algorithm for obtaining acceptable and possibly good university timetables. Some known parallelisation techniques are introduced and the chosen implementation using MPI platform is shown. The master-slave management structure is assumed and the system scalability and the solution quality as function of the processing node number and population size are estimated","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122266460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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