{"title":"将DSP算法映射到FPGA","authors":"O. Maslennikov, A. Sergyienko","doi":"10.1109/PARELEC.2006.51","DOIUrl":null,"url":null,"abstract":"A method of mapping DSP algorithms into FPGA devices is considered. Algorithms are represented by synchronous data flow graphs, and are mapped into pipelined data path. The method consists of placing the algorithm graph in the multidimensional index space and mapping it into structure and event subspaces. The special limitations, which are injected to the mapping process, minimize both clock time and hardware volume including multiplexer inputs","PeriodicalId":186915,"journal":{"name":"International Conference on Parallel Computing in Electrical Engineering","volume":"99 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"Mapping DSP Algorithms into FPGA\",\"authors\":\"O. Maslennikov, A. Sergyienko\",\"doi\":\"10.1109/PARELEC.2006.51\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A method of mapping DSP algorithms into FPGA devices is considered. Algorithms are represented by synchronous data flow graphs, and are mapped into pipelined data path. The method consists of placing the algorithm graph in the multidimensional index space and mapping it into structure and event subspaces. The special limitations, which are injected to the mapping process, minimize both clock time and hardware volume including multiplexer inputs\",\"PeriodicalId\":186915,\"journal\":{\"name\":\"International Conference on Parallel Computing in Electrical Engineering\",\"volume\":\"99 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Parallel Computing in Electrical Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PARELEC.2006.51\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Parallel Computing in Electrical Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PARELEC.2006.51","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A method of mapping DSP algorithms into FPGA devices is considered. Algorithms are represented by synchronous data flow graphs, and are mapped into pipelined data path. The method consists of placing the algorithm graph in the multidimensional index space and mapping it into structure and event subspaces. The special limitations, which are injected to the mapping process, minimize both clock time and hardware volume including multiplexer inputs
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