2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第7页

1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method 一阶到二阶阈值逻辑门变换与一种增强的基于ilp的辨识方法

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431558

Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou

引用次数: 0

Energy and QoS-Aware Dynamic Reliability Management of IoT Edge Computing Systems 物联网边缘计算系统的能量和qos感知动态可靠性管理

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431612

Kazim Ergun, R. Ayoub, Pietro Mercati, D. Liu, T. Simunic

{"title":"Energy and QoS-Aware Dynamic Reliability Management of IoT Edge Computing Systems","authors":"Kazim Ergun, R. Ayoub, Pietro Mercati, D. Liu, T. Simunic","doi":"10.1145/3394885.3431612","DOIUrl":"https://doi.org/10.1145/3394885.3431612","url":null,"abstract":"The Internet of Things (IoT) systems, as any electronic or mechanical system, are prone to failures. Hard failures in hardware due to aging and degradation are particularly important since they are irrecoverable, requiring maintenance for the replacement of defective parts, at high costs. In this paper, we propose a novel dynamic reliability management (DRM) technique for IoT edge computing systems to satisfy the Quality of Service (QoS) and reliability requirements while maximizing the remaining energy of the edge device batteries. We formulate a state-space optimal control problem with a battery energy objective, QoS, and terminal reliability constraints. We decompose the problem into low-overhead subproblems and solve it employing a hierarchical and multi-timescale control approach, distributed over the edge devices and the gateway. Our results, based on real measurements and trace-driven simulation demonstrate that the proposed scheme can achieve a similar battery lifetime compared to the state-of-the-art approaches while satisfying reliability requirements, where other approaches fail to do so.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126882470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Current-Starved Chaotic Oscillator Over Multiple Frequency Decades on Low-Cost CMOS : Towards Distributed and Scalable Environmental Sensing with a Myriad of Nodes 低成本CMOS上多频率数十年的电流匮乏混沌振荡器:面向具有无数节点的分布式和可扩展环境传感

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431651

K. K. Tokgoz, L. Minati, Hiroyuki Ito

引用次数: 0

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization 阅读你的电路:利用词嵌入来指导逻辑优化

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431560

Walter Lau Neto, Matheus T. Moreira, L. Amarù, Cunxi Yu, P. Gaillardon

引用次数: 7

Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme 扩展寄存器重用方案中寄存器实例使用预测和分时寄存器

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431412

Shuxin Zhou, Huandong Wang, Dong Tong

引用次数: 0

DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures DP-Sim:一种全栈内存架构数字处理仿真基础设施

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431525

Minxuan Zhou, M. Imani, Yeseong Kim, Saransh Gupta, T. Simunic

{"title":"DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures","authors":"Minxuan Zhou, M. Imani, Yeseong Kim, Saransh Gupta, T. Simunic","doi":"10.1145/3394885.3431525","DOIUrl":"https://doi.org/10.1145/3394885.3431525","url":null,"abstract":"Digital processing in-memory (DPIM) is a promising technology that significantly reduces data movements while providing high parallelism. In this work, we design and implement the first full- stack DPIM simulation infrastructure, DP-Sim, which evaluates a comprehensive range of DPIM-specific design space concerning both software and hardware. DP-Sim provides a C++ library to enable DPIM acceleration in general programs while supporting several aspects of software-level exploration by a convenient interface. The DP-Sim software front-end generates specialized instructions that can be processed by a hardware simulator based on a new DPIM-enabled architecture model which is 10.3% faster than conventional memory simulation models. We use DP-Sim to explore the DPIM-specific design space of acceleration for various emerging applications. Our experiments show that bank-level control is 11.3 faster than conventional channel-level control because of higher computing parallelism. Furthermore, cost-aware memory allocation can provide at least 2.2 speedup vs. heuristic methods, showing the importance of data layout in DPIM acceleration.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123257952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A General Equivalence Checking Framework for Multivalued Logic 多值逻辑的一般等价检验框架

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431588

Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen, Yung-Chih Chen, Chun-Yao Wang

引用次数: 0

A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna 具有直接调制数字发射机、正交相耦合频率合成器和基板集成波导e型贴片天线的高集成节能CMOS毫米波收发器

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431652

W. Deng, Zheng Song, Ruichang Ma, Haikun Jia, B. Chi

引用次数: 0

RIME: A Scalable and Energy-Efficient Processing-In-Memory Architecture for Floating-Point Operations RIME:用于浮点运算的可伸缩且节能的内存处理体系结构

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431524

Zhaojun Lu, Md Tanvir Arafin, G. Qu

{"title":"RIME: A Scalable and Energy-Efficient Processing-In-Memory Architecture for Floating-Point Operations","authors":"Zhaojun Lu, Md Tanvir Arafin, G. Qu","doi":"10.1145/3394885.3431524","DOIUrl":"https://doi.org/10.1145/3394885.3431524","url":null,"abstract":"Processing in-memory (PIM) is an emerging technology poised to break the memory-wall in the conventional von Neumann architecture. PIM reduces data movement from the memory systems to the CPU by utilizing memory cells for logic computation. However, existing PIM designs do not support high precision computation (e.g., floating-point operations) essential for critical data-intensive applications. Furthermore, PIM architectures require complex control module and costly peripheral circuits to harness the full potential of in-memory computation. These peripherals and control modules usually suffer from scalability and efficiency issues.Hence, in this paper, we explore the analog properties of the resistive random access memory (RRAM) crossbar and propose a scalable RRAM-based in-memory floating-point computation architeture (RIME). RIME uses single-cycle NOR, NAND, and Minority logic to achieve floating-point operations. RIME features a centralized control module and a simplified peripheral circuit to eliminate data movement during parallel computation. An experimental 32-bit RIME multiplier demonstrates 4.8X speedup, 1.9X area-improvement, and 5.4X energy-efficiency than state-of-the-art RRAM-based PIM multipliers.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127966226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy 基于数据增强策略的宽电压设计时序预测框架

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431582

Peng Cao, Wei Bao, Kai Wang, Tai Yang

{"title":"A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy","authors":"Peng Cao, Wei Bao, Kai Wang, Tai Yang","doi":"10.1145/3394885.3431582","DOIUrl":"https://doi.org/10.1145/3394885.3431582","url":null,"abstract":"Wide voltage design has been widely used to achieve power reduction and energy efficiency improvement. The consequent increasing number of PVT corners poses severe challenges to timing analysis in terms of accuracy and efficiency. The data insufficiency issue during path delay acquisition raises the difficulty for the training of machine learning models, especially at low voltage corners due to tremendous library characterization effort and/or simulation cost. In this paper, a learning-based timing prediction framework is proposed to predict path delays across wide voltage region by LightGBM (Light Gradient Boosting Machine) with data augmentation strategies including CTGAN (Conditional Generative Adversarial Networks) and SMOTER (Synthetic Minority Oversampling Technique for Regression), which generate realistic synthetic data of circuit delays to improve prediction precision and reduce data sampling effort. Experimental results demonstrate that with the proposed framework, the path delays at low voltage could be predicted by their delays at high voltage corners with rRMSE of less than 5%, owing to the data augmentation strategies which achieve significant prediction error reduction by up to 12×.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132527814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5