2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)最新文献_第2页

A formal approach to the mapping of tasks on an heterogenous multicore, energy-aware architecture 一种在异构多核、能量感知架构上映射任务的形式化方法

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797760

Emilien Kofman, R. Simone

{"title":"A formal approach to the mapping of tasks on an heterogenous multicore, energy-aware architecture","authors":"Emilien Kofman, R. Simone","doi":"10.1109/MEMCOD.2016.7797760","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797760","url":null,"abstract":"The search for optimal mapping of application (tasks) onto processor architecture (resources) is always an acute issue, as new types of heterogeneous multicore architectures are being proposed constantly. The physical allocation and temporal scheduling can be attempted at a number of levels, from abstract mathematical models and operational research solvers, to practical simulation and run-time emulation. This work belongs to the first category. As often in the embedded domain we take as optimality metrics a combination of power consumption (to be minimized) and performance (to be maintained). One specificity is that we consider a dedicated architecture, namely the big.LITTLE ARM-based platform style that is found in recent Android smartphones. So now tasks can be executed either on fast, energy-costly cores, or slower energy-sober ones. The problem is even more complex since each processor may switch its running frequency, which is a natural trade-off between performance and power consumption. We consider also energy bonus when a full block (big or LITTLE) can be powered down. This dictates in the end a specific set of requirements and constraints, expressed with equations and inequations of a certain size, which must be fed to an appropriate solver (SMT solver in our case). Our original aim was (and still is) to consider whether these techniques would scale up in this case. We conducted experiments on several examples, and we describe more thoroughly a task graph application based on the tiled Cholesky decomposition algorithm, for its relevant size complexity. We comment on our findings and the modeling issues involved.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126709772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Formal feature analysis of hybrid automata 混合自动机的形式特征分析

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797740

Antonio Anastasio Bruto da Costa, P. Dasgupta, Goran Frehse

引用次数: 4

Frame conditions in symbolic representations of UML/OCL models UML/OCL模型的符号表示中的框架条件

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797747

Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, R. Wille, R. Drechsler

{"title":"Frame conditions in symbolic representations of UML/OCL models","authors":"Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, R. Wille, R. Drechsler","doi":"10.1109/MEMCOD.2016.7797747","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797747","url":null,"abstract":"Verification and validation of UML/OCL models is a crucial task in the design of complex software/hardware systems. The behavior in those models is expressed in terms of operations with pre- and postconditions. These, however, are often not precise enough to describe what may or may not be modified in a transition between two system states. This frame problem is commonly addressed by providing additional constraints in terms of so-called frame conditions and has already been considered in different research areas in the last decades - except for UML/OCL where corresponding approaches have been investigated only recently. Besides that, several approaches for the verification of the behavior specified in UML/OCL models have been proposed. They rely on a symbolic representation of all possible system states and transitions between them. But here, frame conditions have not been considered yet - a significant drawback for the underlying verification approaches. In this paper, we describe how to integrate frame conditions to symbolic representations. This enables designers to verify the behavior of UML/OCL models while, at the same time, respecting the given frame conditions.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126574881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Combining type-checking with model-checking for system verification 结合类型检查和模型检查进行系统验证

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797745

Zhiqiang Ren, H. Xi

引用次数: 1

Towards integrating statistical model checking into property-based testing 将统计模型检查集成到基于属性的测试中

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797748

B. Aichernig, Richard Schumi

引用次数: 5

SmashClean: A hardware level mitigation to stack smashing attacks in OpenRISC SmashClean: OpenRISC中堆栈粉碎攻击的硬件级缓解

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797764

Manaar Alam, Debapriya Basu Roy, Sarani Bhattacharya, Vidya Govindan, R. Chakraborty, Debdeep Mukhopadhyay

引用次数: 7

Optimal compilation for exposed datapath architectures with buffered processing units by SAT solvers 利用SAT求解器对带缓冲处理单元的暴露数据路径体系结构进行优化编译

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797759

Anoop Bhagyanath, K. Schneider

{"title":"Optimal compilation for exposed datapath architectures with buffered processing units by SAT solvers","authors":"Anoop Bhagyanath, K. Schneider","doi":"10.1109/MEMCOD.2016.7797759","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797759","url":null,"abstract":"Conventional processor architectures are restricted in exploiting instruction level parallelism (ILP) due to the limited number of available registers in their instruction sets. Therefore, recent processor architectures expose their datapaths so that the compiler not only schedules instructions to functional units, but also takes care of directly moving values between functional units avoiding the need of registers at all. However, the current compiler technology is still based on classic register architectures where a nearly optimal register mapping is the key for the quality of the generated assembly code. The Synchronous Control Asynchronous Dataflow (SCAD) architecture is a new exposed datapath architecture where processing units (PUs) are equipped with first-in first-out (FIFO) buffers at their inputs and outputs. Code generation for SCAD machines can be done as known for classic queue machines to completely eliminate the use of registers, and to improve the degree of exploited ILP. However, the SCAD code generated this way is not optimal since compared to queue machines, SCAD machines can contain many PUs and buffers which offers the compiler more freedom to reduce unnecessary computational overhead. In this paper, we map the SCAD code generation problem to a satisfiability problem, and then use SAT solvers to generate code without overhead that works with the minimal number of PUs. The generated optimal code will serve as a reference to judge the quality of heuristics that will be finally used in SCAD compilers.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114762596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Asynchrony-aware static analysis of Android applications Android应用的异步感知静态分析

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797761

Ashish Mishra, Aditya Kanade, Y. Srikant

{"title":"Asynchrony-aware static analysis of Android applications","authors":"Ashish Mishra, Aditya Kanade, Y. Srikant","doi":"10.1109/MEMCOD.2016.7797761","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797761","url":null,"abstract":"Software applications developed for the Android platform are very popular. Due to this, static analysis of these applications has received a lot of attention recently. An Android application is essentially an asynchronous, event-driven program. The Android framework manages the state of the application by invoking callbacks, called lifecycle callbacks, in pre-defined orders. Unfortunately, the existing static analysis techniques treat the callbacks synchronously. Additionally, they do not model all possible orderings of lifecycle callbacks. These may result in unsound analysis results. In this work, we present a precise representation of control flow of Android applications called Android inter-component control flow graph (AICCFG). In this representation, the asynchronous nature of the callbacks is modeled accurately. Further, all interleavings of callbacks of different components of an Android application are modeled in AICCFG. We use this representation to design a typestate analysis of Android applications. Android applications use a rich set of resources such as camera and media player whose safe usage is governed by some state machines. Using the typestate analysis, we can verify whether an application uses a resource safely or not. We have implemented the construction of AICCFG and the typestate analysis in the Soot framework. We have also implemented a variant of typestate analysis which uses the unsound control flow model used commonly in the literature. To compare our AICCFG based analysis with this, we present a benchmark of Android applications called AsyncBench. It comprises applications that use various resources in both safe and unsafe manner. The experiments over this benchmark demonstrate the benefits of our more precise control flow model and the typestate analysis.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126660103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Formal engineering frameworks in maritime domain awareness 海洋领域感知的形式化工程框架

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797746

A. Shahir, U. Glässer, H. Y. Shahir, M. A. Tayebi, H. Wehn

引用次数: 2

Step revision in hybrid Co-simulation with FMI FMI混合联合仿真的步骤修正

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Pub Date : 2016-11-18 DOI: 10.1109/MEMCOD.2016.7797762

Fabio Cremona, Marten Lohstroh, David Broman, M. Natale, Edward A. Lee, S. Tripakis

引用次数: 21