{"title":"The Diagnosis of Asynchronous Sequential Switching Systems","authors":"S. Seshu, D. N. Freeman","doi":"10.1109/TEC.1962.5219384","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219384","url":null,"abstract":"This paper considers the problem of automatically testing a sequential switching circuit. It is assumed that the sequential circuit is nonclocked in order that the same automatic tester may be used for a wide class of circuits. The program for the tester is to be generated by an IBM 7090 computer from the logical description of the circuit to be tested. The specific problem considered here is to write a program for the 7090 in order to accomplish this purpose. A method of solution and a brief description of the program are given and a worked example is supplied.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"549 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123383558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Division and Overflow Detection in Residue Number Systems","authors":"Yates A. Keir, P. W. Cheney, M. Tannenbaum","doi":"10.1109/TEC.1962.5219389","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219389","url":null,"abstract":"Residue arithmetic has some intriguing characterThe sign of an integer I will be represented implicistics which could possibly be exploited in a special purpose, or even itly: a general purpose, computer. However, simple mechanizations of the operations of division and overflow detection are not inherent in _ < I <-¢ I is ositive the structure of a residue number system. Methods of handling these 2 P operations are discussed in this paper. In the first section, a relatively straightforward division process is presented whose execution time M is comparable to those of existing binary machines. The next section -< I < M X I is negative. shows how the division process can be cut short under certain condi2 M-I. tions. The amount of equipment required for this is not insignificant; however, this equipment can also be used to speed up the normal diviThe integer value of a number W will be designated sion procedure and to detect multiplicative overflow. The multiplicaby [W]. tive overflow detection scheme proposed in the concluding section has Er o the following desirable features: E(I) = 1092(I 1) It does not require a redundant number system. T(I) -2E 2) It is compatible with the division process and requires no Y| X signifies that Y divides X evenly; i.e., X is special circuitry. divisible by Y. If X is not divisible by Y, this is 3) It is faster than the brute-force approaches which either redenoted by Y| /X. quire residue division or essentially check the residue multi(Y, mi) =1 signifies that Y and mi are relatively plication by a multiplication in a more conventional number v system. prime.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116921722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Control Units for Sequencing Complex Asynchronous Operations","authors":"A. Grasselli","doi":"10.1109/TEC.1962.5219387","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219387","url":null,"abstract":"Sequential circuits techniques for the synthesis of digital-computer-control units are investigated. The assumption is made that the operations to be controlled are complex sequences of asynchronous events linked by precedence relations. An algorithm for the synthesis of the control unit flow table from the list of precedence statements is given.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130208183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Programmed Algorithm for Assigning Internal Codes to Sequential Machines","authors":"D. Armstrong","doi":"10.1109/TEC.1962.5219385","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219385","url":null,"abstract":"A relatively fast procedure for assigning codes to the internal states of a sequential machine is described, which leads to a reasonably economical logical realization of the machine in many cases. The method is applicable to both completely and incompletely specified state tables, and permits the use of redundant internal variables if desired. An algorithm which implements the method approximately, and which is nonenumerative, has been programmed for the 7090 computer. The program handles problems with up to 100 internal states and 30 input symbols, or 3000 total states. It has performed a problem of maximum size in 120 seconds. Although fast, the method sometimes fails to attain truly economical logic in cases where unusually simple realizations are known to exist (e.g., the shift register). More comprehensive methods are now known, which in principle can produce better results, but which will be far more tedious to execute. They will be reported separately.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127590853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Correction to \"Two-Level Correlation of an Analog Computer\"","authors":"Carl L. Becker, J. Wait","doi":"10.1109/TEC.1962.5219408","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219408","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114982758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Computer Circuits Using Linear Programming Techniques","authors":"G. H. Goldstick, David G. Mackie","doi":"10.1109/TEC.1962.5219392","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219392","url":null,"abstract":"A step-by-step procedure is presented for formulating circuit synthesis problems in a manner amenable to solution using linear programming. A method of systematizing component value determination using linear programming is explained. The design equations and conditions required to synthesize a diode-coupled inverter and a design procedure for achieving an optimum circuit are presented. The Simplex Method is used to determine component values such that power dissipation is minimized.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122121123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Analog Computer Realization of the Euclidean Tools","authors":"R. Keller","doi":"10.1109/TEC.1962.5219397","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219397","url":null,"abstract":"The compass and straightedge of Euclidean geometry offer many computational possibilities. Their analog computer realization as described here was developed for the study of the kinematics of machinery, but may be useful in several other areas. For the particular case discussed it was necessary to realize these tools without the use of special electronic devices and to make them available for simultaneous use at an arbitrary number of locations. Low operating frequencies were acceptable. The realization utilizes dynamic computing equipment to generate a reference circle or line, and simple logic in the utilization of the reference. The system may be extended to function generation and multiplication.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115779095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Technique for Measuring the Phase Margin of an Operational Amplifier","authors":"H. Handler","doi":"10.1109/TEC.1962.5219399","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219399","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114266609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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