2018 29th Irish Signals and Systems Conference (ISSC)最新文献

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A Comparative Study of Chisel for FPGA Design FPGA设计中凿子的比较研究
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-21 DOI: 10.1109/ISSC.2018.8585292
Paul Lennon, Richard Gahan
{"title":"A Comparative Study of Chisel for FPGA Design","authors":"Paul Lennon, Richard Gahan","doi":"10.1109/ISSC.2018.8585292","DOIUrl":"https://doi.org/10.1109/ISSC.2018.8585292","url":null,"abstract":"This paper presents the results of a comparative study conducted into designing with the Chisel hardware construction language against the Verilog hardware description language across a range of standard-library and bespoke FPGA design components including an N-bit FIFO, a round-robin arbiter and a complex, scalable arbiter. Comparison metrics such as maximum operating frequency, silicon area, design flow run-time, source-code density and maintainability, simulation run-time and speed of coding are employed to evaluate the merits of designing with Chisel. Each component is implemented with a deep low-level hardware understanding with an aim to evaluate the merits of designing with Chisel from a hardware designers’ perspective. The authors discover Chisel’s merits for realising synthesizable repetitive designs such as in SoC development, experiencing the benefits of Chisel’s object-oriented background in enhancing code maintainability and scalability, and implementation efficiency. However, the authors foresee that Chisel will compliment rather than replace traditional HDLs for RTL design applications due to its limitations in terms of behavioural modelling.","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122191304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Machine Vision Approach to Human Activity Recognition using Photoplethysmograph Sensor Data 利用光电容积脉搏波传感器数据进行人体活动识别的机器视觉方法
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-21 DOI: 10.1109/ISSC.2018.8585372
Eoin Brophy, J. J. Dominguez, Zhengwei Wang, T. Ward
{"title":"A Machine Vision Approach to Human Activity Recognition using Photoplethysmograph Sensor Data","authors":"Eoin Brophy, J. J. Dominguez, Zhengwei Wang, T. Ward","doi":"10.1109/ISSC.2018.8585372","DOIUrl":"https://doi.org/10.1109/ISSC.2018.8585372","url":null,"abstract":"Human activity recognition (HAR) is an active area of research concerned with the classification of human motion. Cameras are the gold standard used in this area, but they are proven to have scalability and privacy issues. HAR studies have also been conducted with wearable devices consisting of inertial sensors. Perhaps the most common wearable, smart watches, comprising of inertial and optical sensors, allow for scalable, non-obtrusive studies. We are seeking to simplify this wearable approach further by determining if wrist-mounted optical sensing, usually used for heart rate determination, can also provide useful data for relevant activity recognition. If successful, this could eliminate the need for the inertial sensor, and so simplify the technological requirements in wearable HAR. We adopt a machine vision approach for activity recognition based on plots of the optical signals so as to produce classifications that are easily explainable and interpretable by nontechnical users. Specifically, time-series images of photoplethysmography signals are used to retrain the penultimate layer of a pretrained convolutional neural network leveraging the concept of transfer learning. Our results demonstrate an average accuracy of 75.8%. This illustrates the feasibility of implementing an optical sensor-only solution for a coarse activity and heart rate monitoring system. Implementing an optical sensor only in the design of these wearables leads to a trade off in classification performance, but in turn, grants the potential to simplify the overall design of activity monitoring and classification systems in the future.","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127236207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Switched Capacitor Charge Pump Voltage-Controlled Current Source 开关电容充电泵电压控制电流源
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-01 DOI: 10.1109/ISSC.2018.8585387
Luca Avallone, E. Napoli, Michael Peter Kennedy
{"title":"Switched Capacitor Charge Pump Voltage-Controlled Current Source","authors":"Luca Avallone, E. Napoli, Michael Peter Kennedy","doi":"10.1109/ISSC.2018.8585387","DOIUrl":"https://doi.org/10.1109/ISSC.2018.8585387","url":null,"abstract":"This manuscript describes a switched-capacitor current source for applications such as driving high brightness LEDs and lasers. By introducing a third phase of operation into a two-phase charge pump DC-DC converter, the proposed design offers a potential solution to the excessive power typically consumed in regulating the diode or laser current. This results in a highly integrable voltage-to-current regulator.","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115108992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Accelerating Image Algorithm Development using Soft Co-Processors on FPGAs 利用fpga上的软协处理器加速图像算法开发
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-01 DOI: 10.1109/ISSC.2018.8585363
Tiantai Deng, D. Crookes, R. Woods, F. Siddiqui
{"title":"Accelerating Image Algorithm Development using Soft Co-Processors on FPGAs","authors":"Tiantai Deng, D. Crookes, R. Woods, F. Siddiqui","doi":"10.1109/ISSC.2018.8585363","DOIUrl":"https://doi.org/10.1109/ISSC.2018.8585363","url":null,"abstract":"FPGAs can offer high performance with low power and low hardware usage. However, with current software, FPGAs are hard to program, and lengthy re-synthesis times make them unsuitable for the algorithm experimentation which is typical of developing image processing applications. In this paper, we present a system model based on a set of Soft Co-Processors, each of which implements a basic image-level operation (or a common combination of such operations) based on the high-level operators in Image Algebra. Both ‘debug’ (generic but unoptimised) and ‘release’ (specific and optimised) versions of the Soft Co-Processors can be used. The advantage of debug mode is that no re-synthesis is required during algorithm experimentation. For release mode, a novel macro-based transformation tool enables the creation of a set of reusable HLS skeleton co-processors which require the user only to write a C function to obtain a new, special-purpose Soft Co-Processor.Initial experiments with several algorithms show that the area and speed overheads for using debug (rather than release) mode are both around 25-30%, thus enabling algorithm development to take place on the FPGA itself. For creating function-specific Co-processors using our macro-based tool, the overheads compared with an expert hardware design are around 20%.","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114101374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
[Copyright notice] (版权)
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-01 DOI: 10.1109/issc.2018.8585290
{"title":"[Copyright notice]","authors":"","doi":"10.1109/issc.2018.8585290","DOIUrl":"https://doi.org/10.1109/issc.2018.8585290","url":null,"abstract":"","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Information Hiding using Convolutional Encoding 使用卷积编码的信息隐藏
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-01 DOI: 10.21427/D72529
J. Blackledge, P. Tobin, J. Myeza, Cid Mathew Adolfo
{"title":"Information Hiding using Convolutional Encoding","authors":"J. Blackledge, P. Tobin, J. Myeza, Cid Mathew Adolfo","doi":"10.21427/D72529","DOIUrl":"https://doi.org/10.21427/D72529","url":null,"abstract":"We consider two functions f1(r) and f2(r), for r ∈ ℝn and the problem of ‘Diffusing’ these functions together, followed by the application of an encryption process we call ‘Stochastic Diffusion’ and then hiding the output of this process in to one or other of the same functions. The coupling of these two processes (i.e., data diffusion and stochastic diffusion) is considered using a form of conditioning that generates a well-posed and data consistent inverse solution for the purpose of decrypting the output.After presenting the basic encryption method and (encrypted) information hiding model, coupled with a mathematical analysis (within the context of ‘convolutional encoding’), we provide a case study which is concerned with the implementation of the approach for full-colour 24-bit digital images. The ideas considered yields the foundations for a number of wide-ranging applications that include covert signal and image information interchange, data authentication, copyright protection and digital rights management, for example.","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128957958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test methodology for measuring resistance and capacitance leakage current in Integrated Compensators Intended for Automotive Applications 测量汽车用集成补偿器中电阻和电容泄漏电流的试验方法
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-01 DOI: 10.1109/ISSC.2018.8585339
Stephen Ogunniran, Tallita C. Sobral, P. Napolitano, Ihsan F. I. Albittar
{"title":"Test methodology for measuring resistance and capacitance leakage current in Integrated Compensators Intended for Automotive Applications","authors":"Stephen Ogunniran, Tallita C. Sobral, P. Napolitano, Ihsan F. I. Albittar","doi":"10.1109/ISSC.2018.8585339","DOIUrl":"https://doi.org/10.1109/ISSC.2018.8585339","url":null,"abstract":"In this work, a test methodology is presented, describing how the components of a fully integrated type III compensator have been measured. More in particular, two different methodologies have been implemented, in order to measure the values of the compensator resistances and to measure current leakages through the compensator capacitances. The methodology discussed in this paper has been applied to a type III compensator used in a buck converter, intended for automotive applications and, without loss of generality, can be extended to other types of compensators and voltage regulators.","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132860675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reducing the intrusion of user-trained activity recognition systems 减少用户训练的活动识别系统的入侵
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-01 DOI: 10.1109/ISSC.2018.8585343
William Duffy, K. Curran, D. Kelly, T. Lunney
{"title":"Reducing the intrusion of user-trained activity recognition systems","authors":"William Duffy, K. Curran, D. Kelly, T. Lunney","doi":"10.1109/ISSC.2018.8585343","DOIUrl":"https://doi.org/10.1109/ISSC.2018.8585343","url":null,"abstract":"Many supervised activity recognition systems require a fully labelled time-series for accurate classification. However, gathering these labels is a difficult and often unrealistic task, especially over long-time frames or outside of laboratory conditions. A potential solution is through diary studies, allowing for a user-trained activity recognition system. Requests will be presented on the user’s smart device and while this approach will be significantly less intrusive than current methods, frequent or inappropriately timed requests could reduce user acceptance. This paper proposes to further reduce user intrusion by making a prediction about the next user request and analyzing the classifiers confidence in this prediction. Two methods are presented, and with careful selection of the confidence threshold, they resulted in up to a 35% reduction in user requests with a minimal reduction in accuracy.","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130806523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power analysis of sorting algorithms on FPGA using OpenCL 基于OpenCL的FPGA上排序算法功耗分析
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-01 DOI: 10.1109/ISSC.2018.8585361
Aidan O. Mahony, E. Popovici
{"title":"Power analysis of sorting algorithms on FPGA using OpenCL","authors":"Aidan O. Mahony, E. Popovici","doi":"10.1109/ISSC.2018.8585361","DOIUrl":"https://doi.org/10.1109/ISSC.2018.8585361","url":null,"abstract":"With the advent of big data and cloud computing, there is tremendous interest in optimised algorithms and architectures for sorting either using software or hardware. Field Programmable Gate Arrays(FPGAs) are being increasingly used in high end data servers providing a bridge between the flexibility of software and performance benefits of hardware. In this paper we look at implementations of some of the most popular sorting algorithms using OpenCL which take advantage of FPGA architecture. We evaluate these implementations in terms of power consumption which is measured using dedicated server power loggers and execution on Intel Arria 10 hardware. Our experiments show that taking advantage of software FIFOs have a significant impact on power consumption as well as requiring less hardware and memory resources.","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123004639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ISSC 2018 Plenary Talks ISSC 2018全体会议
2018 29th Irish Signals and Systems Conference (ISSC) Pub Date : 2018-06-01 DOI: 10.1109/issc.2018.8585385
{"title":"ISSC 2018 Plenary Talks","authors":"","doi":"10.1109/issc.2018.8585385","DOIUrl":"https://doi.org/10.1109/issc.2018.8585385","url":null,"abstract":"","PeriodicalId":174854,"journal":{"name":"2018 29th Irish Signals and Systems Conference (ISSC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116711779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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