{"title":"Advanced Concepts and Architectures for Plasma-Enabled Material Processing","authors":"O. Baranov, I. Levchenko, Shuyan Xu, K. Bazaka","doi":"10.2200/S01042ED1V01Y202008EET011","DOIUrl":"https://doi.org/10.2200/S01042ED1V01Y202008EET011","url":null,"abstract":"Plasma-based techniques are widely and successfully used across the field of materials processing, advanced nanosynthesis, and nanofabrication. The diversity of currently available processing architectures based on or enhanced by the use of plasmas is vast, and one can easily get lost in the opportunities presented by each of these configurations. This mini-book provides a concise outline of the most important concepts and architectures in plasma-assisted processing of materials, helping the reader navigate through the fundamentals of plasma system selection and optimization. Architectures discussed in this book range from the relatively simple, user-friendly types of plasmas produced using direct current, radio-frequency, microwave, and arc systems, to more sophisticated advanced systems based on incorporating and external substrate architectures, and complex control mechanisms of configured magnetic fields and distributed plasma sources.","PeriodicalId":172443,"journal":{"name":"Synthesis Lectures on Emerging Engineering Technologies","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115780452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low Substrate Temperature Modeling Outlook of Scaled n-MOSFET","authors":"N. Ashraf","doi":"10.2200/S00858ED1V01Y201805EET010","DOIUrl":"https://doi.org/10.2200/S00858ED1V01Y201805EET010","url":null,"abstract":"Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100‒300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 𝜇m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temper ture operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.","PeriodicalId":172443,"journal":{"name":"Synthesis Lectures on Emerging Engineering Technologies","volume":"45 42","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120811379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}