2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)最新文献_第10页

Compact chaotic oscillator using 1 80nm CMO S technology for its use in true random number generator 紧凑的混沌振荡器采用1800nm cmos技术用于真随机数发生器

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378183

M. Priya, G. Swetha, Ramji Gupta, Alpana Pandey

引用次数: 2

Design of dual band and dual mode microstrip patch antennan for using wireless communication 用于无线通信的双频双模微带贴片天线的设计

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378130

R. Pal, D. Agrawal

引用次数: 0

2 × 2 microstrip patch antenna array fed by substrate integrated waveguide for radar applications 雷达用基板集成波导馈电的2 × 2微带贴片天线阵列

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/rise.2017.8378131

Chandani Baranwal

引用次数: 19

A novel method of model reduction in linear systems using big bang big crunch optimization and routh pade approximant 利用大爆炸大压缩优化和growth page近似的线性系统模型约简新方法

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378151

Priyanka Thakur, D. Chandra

引用次数: 0

Radiation hardened by design technique to mitigate single event transients in combinational logic circuits 组合逻辑电路中单事件瞬变的强化辐射设计技术

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378178

Tokala Vinay Reddy, Sangeeta Nakhate

{"title":"Radiation hardened by design technique to mitigate single event transients in combinational logic circuits","authors":"Tokala Vinay Reddy, Sangeeta Nakhate","doi":"10.1109/RISE.2017.8378178","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378178","url":null,"abstract":"Single event transients (SETs) have become increasingly problematic for both combinational and sequential VLSI circuits in the deep submicron technology (DSM). This is due to continuously decreasing feature sizes, lower supply voltages and higher operating frequencies. Many critical applications such as biomedical, space and military electronics as well as several mainstream computing applications demand reliable circuit functionality. Therefore, the circuits used in these application must be tolerant to SEU/SET events and therefore, these circuits are designed using circuit hardening approaches. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on combinational logic circuits. It presents a Radiation Hardened By Design (RHBD) of combinational circuits using 0.18μm technology and developed with the help of Cadence tool. This design style achieves SET mitigation by using C element and strengthening the sensitive output node. In order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability with minimum area, power and speed penalties.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115858218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Physical design, implementatation and FFT analysis of multistage differential amplifiers circuits using C5 process for deep submicron CMOS 基于C5工艺的深亚微米CMOS多级差分放大电路的物理设计、实现和FFT分析

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378197

Shreya Barsiya, Ayoush Johari, Soni Changlani

{"title":"Physical design, implementatation and FFT analysis of multistage differential amplifiers circuits using C5 process for deep submicron CMOS","authors":"Shreya Barsiya, Ayoush Johari, Soni Changlani","doi":"10.1109/RISE.2017.8378197","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378197","url":null,"abstract":"The differential amplifier is mostly used as an input to allow supply voltages to propagate so that further gain stages in operational amplifier which are also function of input biasing voltages didn't get affected. The differential amplifiers are also fundamental building block of advanced analog integrated circuits in our presented design multistage operational amplifier design. Design presented in this paper is a multistage CMOS differential amplifiers and time and frequency analysis of the same is also carried out and evaluated the effect of various parameters on the characteristics of differential amplifier, which operates at suitable biasing sources using C5 process for scalable CMOS technology. Differential amplifier design presented here in this paper will be implemented using Electric VLSI 9.06. Simulation outcomes and further analysis is tabulated using LTSpiceXVII. There are numerous number of configurations for operational amplifier exists in literature. The presented designs will also define the operating characteristics of differential amplifiers; a brief comparison is also presented for operating point analysis for multiple stage operational amplifiers. FFT analysis is also done for better noise index results. Here parameters are computed and response curves are computed.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121050883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Comparison of LSB methods and pattern LSB方法和模式的比较

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378162

J. Bharti, Surendra Solanki, Ankit Beliya

引用次数: 3

Comparative study of MSVD, PCA, DCT, DTCWT, SWT and Laplacian Pyramid based image fusion 基于MSVD、PCA、DCT、DTCWT、SWT和拉普拉斯金字塔的图像融合比较研究

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378165

Prashant Dwivedy, A. Potnis, Shahbaz Soofi, Madhuram Mishra

引用次数: 4

Comparative analysis of FEC subsystem in fixed satellite broadcasting standards 卫星固定广播标准中FEC分系统的比较分析

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378119

Abha Jain, R. Singhai

引用次数: 2

WSN assisted modulation detection with maximum likelihood approach, suitable for non-identical Rayleigh channels 基于最大似然方法的无线传感器网络辅助调制检测，适用于非相同瑞利信道

2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) Pub Date : 2017-10-01 DOI: 10.1109/RISE.2017.8378123

Sudhanshu Arya, S. Yadav, S. K. Patra

{"title":"WSN assisted modulation detection with maximum likelihood approach, suitable for non-identical Rayleigh channels","authors":"Sudhanshu Arya, S. Yadav, S. K. Patra","doi":"10.1109/RISE.2017.8378123","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378123","url":null,"abstract":"Adaptive modulation plays an important role inoptimum spectrum utilization. In adaptive modulation, the transmitter dynamically changes the modulation scheme based on the channel state information CSI). The receiver must know the type of modulation used in order to demodulate the received signal. In this paper, the likelihood-based modulation detection using power efficient single hop wireless sensor network (WSN) is presented. The local estimation of the modulation scheme used and channel state information is performed at each sensor. Eachsensor is assumed to experience non-identical Rayleigh fading channel. Each sensor performs two operations, its local maximum-likelihood (ML) based channel estimation and the evaluation of the local likelihood functions of the received noisy signal under all possible modulation hypothesis, adaptively used at the transmitter. These local likelihood functions from all the sensors are fed into the master node for global classification. The power-efficient single-hop fusion technique is employed to fuse the local data into the master node. The performance of the proposed approach is evaluated using the probability of correct classification, Pcc, and the time complexity.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129779659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3