Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献_第4页

Modeling switching activity using cascaded Bayesian networks for correlated input streams 对相关输入流使用级联贝叶斯网络建模交换活动

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106799

S. Bhanja, N. Ranganathan

引用次数: 8

Environment synthesis for compositional model checking 用于构件模型检验的环境综合

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106750

Hong Peng, Y. Mokhtari, S. Tahar

引用次数: 15

On the coverage of delay faults in scan designs with multiple scan chains 多扫描链扫描设计中延迟故障的覆盖

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106771

I. Pomeranz, S. Reddy

引用次数: 8

Power analysis of bipartition and dual-encoding architecture for pipelined circuits 流水线电路双分割双编码结构的功耗分析

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106790

S. Ruan, E. Naroska, Chia-Lin Ho, F. Lai

引用次数: 0

Fault dictionary size reduction through test response superposition 通过测试响应叠加减少故障字典大小

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106817

B. Arslan, A. Orailoglu

引用次数: 20

Media processing applications on the Imagine stream processor Imagine流处理器上的媒体处理应用程序

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106785

John Douglas Owens, S. Rixner, U. Kapasi, P. Mattson, Brian Towles, B. Serebrin, W. Dally

引用次数: 88

A framework for data prefetching using off-line training of Markovian predictors 使用离线训练马尔可夫预测器的数据预取框架

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106792

Jinwoo Kim, K. Palem, W. Wong

{"title":"A framework for data prefetching using off-line training of Markovian predictors","authors":"Jinwoo Kim, K. Palem, W. Wong","doi":"10.1109/ICCD.2002.1106792","DOIUrl":"https://doi.org/10.1109/ICCD.2002.1106792","url":null,"abstract":"An important technique for alleviating the memory bottleneck is data prefetching. Data prefetching solutions ranging from pure software approach by inserting prefetch instructions through program analysis to purely hardware mechanisms have been proposed. The degrees of success of those techniques are dependent on the nature of the applications. The need for innovative approach is rapidly growing with the introduction of applications such as object-oriented applications that show dynamically changing memory access behavior In this paper, we propose a novel framework for the use of data prefetchers that are trained off-line using smart learning algorithms to produce prediction models which captures hidden memory access patterns. Once built, those prediction models are loaded into a data prefetching unit in the CPU at the appropriate point during the runtime to drive the prefetching. On average by using table size of about 8KB size, we were able to achieve prediction accuracy of about 68% through our own proposed learning method and performance was boosted about 37% on average on the benchmarks we tested. Furthermore, we believe our proposed framework is amenable to other predictors and can be done as a phase of the profiling-optimizing-compiler.","PeriodicalId":164768,"journal":{"name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128153762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding 基于双LFSR重播掩模模式生成的低功耗混合模式BIST

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106816

P. Rosinger, B. Al-Hashimi, N. Nicolici

引用次数: 60

Automotive virtual integration platforms: why's, what's, and how's 汽车虚拟集成平台:为什么，是什么，以及如何

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106796

P. Giusto, J. Brunel, A. Ferrari, E. Fourgeau, L. Lavagno, A. Sangiovanni-Vincentelli

引用次数: 32

Physical planning of on-chip interconnect architectures 片上互连架构的物理规划

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI: 10.1109/ICCD.2002.1106743

Hongyu Chen, B. Yao, Feng Zhou, Chung-Kuan Cheng

{"title":"Physical planning of on-chip interconnect architectures","authors":"Hongyu Chen, B. Yao, Feng Zhou, Chung-Kuan Cheng","doi":"10.1109/ICCD.2002.1106743","DOIUrl":"https://doi.org/10.1109/ICCD.2002.1106743","url":null,"abstract":"Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand for communication. A multi-commodity flow (MCF) model is proposed to find the throughput for several different routing architectures. The experimental results reveal several trends: 1. The throughput is limited by the capacity of the middle row and column in the mesh, simply enlarging the congested channel cannot produce better throughput. A flexible chip shape provides around 30% throughput improvement over a square chip of equal area. 2. A 45-degree mesh allows 17% throughput improvement over 90-degree mesh and a 90-degree and 45-degree mixed mesh provides 30% throughput improvement. 3. To achieve maximum throughput on a mixed Manhattan and diagonal interconnect architecture, the best ratio of the capacity for diagonal routing layers and the capacity for Manhattan routing layers is 5.6. 4. Incorporating a simplified via model, interleaving diagonal routing layers and Manhattan routing layer is the best way to organize the wiring directions on different layers.","PeriodicalId":164768,"journal":{"name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124359926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7