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Proceedings of the Eighth International Symposium on System Synthesis最新文献

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Clustering for improved system-level functional partitioning 用于改进系统级功能分区的集群
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1109/ISSS.1995.520609
F. Vahid, D. Gajski
{"title":"Clustering for improved system-level functional partitioning","authors":"F. Vahid, D. Gajski","doi":"10.1109/ISSS.1995.520609","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520609","url":null,"abstract":"Partitioning of system functionality for implementation among multiple system components, such as among hardware and software components, is becoming an increasingly important topic. Various heuristics can accomplish such partitioning. We demonstrate that clustering can be used to merge pieces of functionality before applying other heuristics, resulting in reduced runtimes with little or no loss in quality, and often with improvements in quality. In addition, we show that clustering, when used for N-way partitioning, fills the gap between fast heuristics and highly-optimizing heuristics.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133813778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
An approach to interface synthesis 界面合成的一种方法
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1109/ISSS.1995.520607
J. Madsen, B. Hald
{"title":"An approach to interface synthesis","authors":"J. Madsen, B. Hald","doi":"10.1109/ISSS.1995.520607","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520607","url":null,"abstract":"Presents a novel interface synthesis approach based on a one-sided interface description. Whereas most other approaches consider interface synthesis as optimizing a channel to existing client/server modules, we consider the interface synthesis as part of the client/server module synthesis (which may contain the re-use of existing modules). The interface synthesis approach describes the basic transformations needed to transform the server interface description into an interface description on the client side of the communication medium. The synthesis approach is illustrated through a point-to-point communication, but is applicable to synthesis of a multiple client/server environment. The interface description is based on a formalization of communication events.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133140820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Power analysis and low-power scheduling techniques for embedded DSP software 嵌入式DSP软件的功耗分析和低功耗调度技术
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1145/224486.224525
M. Lee, V. Tiwari, S. Malik, M. Fujita
{"title":"Power analysis and low-power scheduling techniques for embedded DSP software","authors":"M. Lee, V. Tiwari, S. Malik, M. Fujita","doi":"10.1145/224486.224525","DOIUrl":"https://doi.org/10.1145/224486.224525","url":null,"abstract":"This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been developed using this technique. Significant points of difference have been observed between this model and the ones developed earlier for some general-purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the DSP processor has a special architectural feature that allows instructions to be packed into pairs. The energy reduction possible through the use of this feature is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A micro-architectural power model for the multiplier is developed and analyzed for further energy minimization. A scheduling algorithm incorporating these new techniques is proposed to reduce the energy consumed by DSP software. Energy reductions varying from 11% to 56% have been observed for several example programs. These energy savings are real and have been verified through physical measurement.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125448071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Scheduling and resource binding for low power 低功耗调度和资源绑定
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1145/224486.224523
E. Musoll, J. Cortadella
{"title":"Scheduling and resource binding for low power","authors":"E. Musoll, J. Cortadella","doi":"10.1145/224486.224523","DOIUrl":"https://doi.org/10.1145/224486.224523","url":null,"abstract":"Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algorithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the functional units (adders, multipliers) by minimizing the transitions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116862019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
Time-constrained code compaction for DSPs dsp的时间约束代码压缩
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1109/ISSS.1995.520613
R. Leupers, P. Marwedel
{"title":"Time-constrained code compaction for DSPs","authors":"R. Leupers, P. Marwedel","doi":"10.1109/ISSS.1995.520613","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520613","url":null,"abstract":"DSP algorithms are, in most cases, subject to hard real-time constraints. In the case of programmable DSPs, meeting those constraints must be ensured by appropriate code generation techniques. For processors offering instruction-level parallelism, the task of code generation includes code compaction. The exact timing behavior of a DSP program is only known after compaction. Therefore, real-time constraints should be taken into account during the compaction phase. While most known DSP code generators rely on rigid heuristics for that phase, this paper proposes a novel approach to local code compaction based on an integer programming model, which obeys exact timing constraints. Due to a general problem formulation, the model also obeys encoding restrictions and possible side-effects.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134519912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis 基于路径的硬件运行时估计技术
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1109/ISSS.1995.520622
J. Henkel, R. Ernst
{"title":"A path-based technique for estimating hardware runtime in HW/SW-cosynthesis","authors":"J. Henkel, R. Ernst","doi":"10.1109/ISSS.1995.520622","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520622","url":null,"abstract":"One of the key issues in hardware/software-cosynthesis is precise estimation. The usual local estimation techniques are inadequate for globally optimising compilers and synthesis tools. We present a path based estimation technique which allows a computation time/quality tradeoff. The results show acceptable computation times while revealing much more potential parallelism than local list scheduling.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123857759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
On the use of VHDL-based behavioral synthesis for telecom ASIC design 基于vhdl的行为综合技术在电信专用集成电路设计中的应用
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1145/224486.224514
M. Genoe, P. Vanoostende, G. V. Wauwe
{"title":"On the use of VHDL-based behavioral synthesis for telecom ASIC design","authors":"M. Genoe, P. Vanoostende, G. V. Wauwe","doi":"10.1145/224486.224514","DOIUrl":"https://doi.org/10.1145/224486.224514","url":null,"abstract":"VHDL-based behavioral synthesis is appearing on the market but it still has to prove that it can have a significant impact. In the past, most applications for behavioral synthesis came from the DSP area and from the academic world. In contrast, this paper describes the results of an investigation and evaluation of several behavioral synthesis tools, carried out on recent designs of Alcatel-Bell, leading to a more detailed study of relevant industrial telecom non-DSP circuits, that were suitable for behavioral synthesis. From our expertise in telecom system hardware design, we can conclude that, taking into account that today world-wide about 6,000 licenses for logic synthesis are in use, there is distinctly a market potential for design-entries at higher levels of abstraction, due to the still increasing design complexities that can be expected in the near future. Behavioral synthesis can play a key role in this prospect, as stand-alone hardware CAD tool, or integrated in a global system design flow strategy for HW/SW-codesign. However, we experienced that efficient use of behavioral synthesis tools for telecom non-DSP circuits requires functionality that goes beyond simply generating an RTL-synthesizable description. This functionality is discussed, together with a system level design methodology for efficient use of behavioral synthesis tools.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125124836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The Chinook hardware/software co-synthesis system 支奴干硬件/软件协同合成系统
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1145/224486.224491
P. Chou, R. Ortega, G. Borriello
{"title":"The Chinook hardware/software co-synthesis system","authors":"P. Chou, R. Ortega, G. Borriello","doi":"10.1145/224486.224491","DOIUrl":"https://doi.org/10.1145/224486.224491","url":null,"abstract":"Designers of embedded systems are facing ever tighter constraints on design time, but computer-aided design tools for embedded systems have not kept pace with these trends. The Chinook co-synthesis system addresses the automation of the most time-consuming and error-prone tasks in embedded controller design, namely the synthesis of interface hardware and software needed to integrate system components, the migration of functions between processors or custom logic, and the co-simulation of the design before, during and after synthesis. This paper describes the principal elements of Chinook and discuss its application to a variety of embedded designs.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116716567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 183
Sensitivity-driven co-synthesis of distributed embedded systems 分布式嵌入式系统的灵敏度驱动协同合成
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1145/224486.224488
Ti-Yen Yen, W. Wolf
{"title":"Sensitivity-driven co-synthesis of distributed embedded systems","authors":"Ti-Yen Yen, W. Wolf","doi":"10.1145/224486.224488","DOIUrl":"https://doi.org/10.1145/224486.224488","url":null,"abstract":"Describes a new, sensitivity-driven algorithm for the co-synthesis of real-time distributed embedded systems. Many embedded computing systems are distributed systems: communicating periodic processes executing on several CPUs/ASICs connected by communication links. We use performance estimates to compute a local sensitivity of the design to process allocation. We propose a priority prediction method to schedule processes. Based on these techniques, we develop a gradient-search algorithm which co-synthesizes heterogeneous distributed systems of arbitrary topology and the associated application software architecture. Experimental results show that our algorithm can find good implementation architectures in small amounts of CPU time.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"4 21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130322882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Procedure exlining: a transformation for improved system and behavioral synthesis 程序检查:为改进系统和行为综合而进行的转换
Proceedings of the Eighth International Symposium on System Synthesis Pub Date : 1995-09-13 DOI: 10.1145/224486.224506
F. Vahid
{"title":"Procedure exlining: a transformation for improved system and behavioral synthesis","authors":"F. Vahid","doi":"10.1145/224486.224506","DOIUrl":"https://doi.org/10.1145/224486.224506","url":null,"abstract":"We present techniques for solving the inverse problem of procedure inlining, namely the problem of replacing sequences of statements with procedure calls. Two techniques are provided, one for finding redundant sequences of statements that can be replaced by calls to one procedure, and another for dividing a large set of statements into several procedures, where each procedure performs a distinct computation. Such procedure exlining can transform a behavioral specification, originally written for readability, into a specification that can be implemented efficiently, because procedures can greatly improve the results of synthesis tools. We demonstrate the usefulness of the techniques on several examples. We have implemented the procedure exlining technique as part of a VHDL transformation tool.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129300425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
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