2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW)最新文献_第2页

CoBaS: Introducing a Component Based Scheduling Framework coba:引入基于组件的调度框架

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.23

Anselm Busse, R. Karnapke, Hans-Ulrich Heiß

{"title":"CoBaS: Introducing a Component Based Scheduling Framework","authors":"Anselm Busse, R. Karnapke, Hans-Ulrich Heiß","doi":"10.1109/SBAC-PADW.2015.23","DOIUrl":"https://doi.org/10.1109/SBAC-PADW.2015.23","url":null,"abstract":"Many-Core systems and heterogeneous systems are getting more and more common and may soon enter the mainstream market. To harvest their capabilities to their full potential, the runtime system's scheduling policies have to be adapted and, in many cases, tailored to the specific system. The runtime system can be both an operating system or management infrastructure of an infrastructure as a service (IaaS) platform. Developing, implementing, and testing those scheduling policies is a challenging task in general. In this work we present CoBaS, a component based scheduling framework for multi and many-core runtime systems. The main purpose of CoBaS is the simplification of the scheduling policy implementation and an increased code reuse to save time during development. CoBaS uses a novel approach to reach that goal. It allows the breakdown of the policy implementation into several components that can be reused. Through composition, a fast prototyping, testing and evaluation of new scheduling policies is possible without implementing every functional part again. CoBaS uses an event based approach to distribute information about system states and state changes between the runtime system and components as well as between components themselves. Furthermore, it has a facility to hand over ordered task sets between components. We have adapted both the Linux and Free BSD kernel to use CoBaS by completely removing the native scheduler. The integration of CoBaS into those kernels shows the feasibility of our approach.","PeriodicalId":161685,"journal":{"name":"2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW)","volume":"224 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120863302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Single-Loop Approach to 2-D Wavelet Lifting with JPEG 2000 Compatibility 单环二维小波提升方法与JPEG 2000兼容

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.10

David Barina, Petr Musil, M. Musil, P. Zemčík

引用次数: 4

MDACCER: Modified Distributed Assessment of the Closeness CEntrality Ranking in Complex Networks for Massively Parallel Environments MDACCER:大规模并行环境下复杂网络亲密度中心性排序的改进分布式评估

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.28

F. L. Cabral, Carla Osthoff, D. Ramos-Castro, Rafael Nardes

{"title":"MDACCER: Modified Distributed Assessment of the Closeness CEntrality Ranking in Complex Networks for Massively Parallel Environments","authors":"F. L. Cabral, Carla Osthoff, D. Ramos-Castro, Rafael Nardes","doi":"10.1109/SBAC-PADW.2015.28","DOIUrl":"https://doi.org/10.1109/SBAC-PADW.2015.28","url":null,"abstract":"We propose a new method derived from DACCER (Distributed Assessment of the Closeness CEntrality Ranking): the modified DACCER (MDACCER), for assessing traditional closeness centrality ranking. MDACCER presents a relaxation that allows it to take advantage of massively parallel environments like General Purpose Graphics Processing Units (GPGPUs). Traditional DACCER proposal assesses Closeness centrality ranking in a limited neighborhood using only information around each node at low computational cost and capability to be executed in a distributed environment. Despite all the advantages, DACCER presents some difficulties in GPGPUs programming model that increases its computational cost at this particular environment. In contrast to the poor performance of DACCER on GPGPUs, experimental results demonstrate MDACCER is as simple and efficient as DACCER to assess Closeness centrality ranking in complex networks and moreover it does not have the same bottlenecks in GPGPUs computing about memory usage and time complexity. We performed MDACCER for some synthetically generated networks, specifically Barabási-Albert ones and results indicate MADCCER correlates Closeness centrality ranking almost as well as DACCER does with lower computational costs.","PeriodicalId":161685,"journal":{"name":"2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132210720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

CHAOS-MCAPI: An Optimized Mechanism to Support Multicore Parallel Programming 混沌- mcapi:支持多核并行编程的优化机制

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.12

Antonio Ideguchi, C. E. Morón, M. M. Fernandes

引用次数: 0

Painless Parallelism on Heterogeneous Hardware Leveraging the Functional Paradigm 利用功能范式在异构硬件上实现无痛并行

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.24

Mauro Blanco, Pablo Perdomo, P. Ezzatti, Alberto Pardo, Marcos Viera

引用次数: 0

Using Hardware Transactional Memory to Enable Speculative Trace Optimization 使用硬件事务性内存启用推测跟踪优化

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.13

Juan Salamanca, J. N. Amaral, G. Araújo

{"title":"Using Hardware Transactional Memory to Enable Speculative Trace Optimization","authors":"Juan Salamanca, J. N. Amaral, G. Araújo","doi":"10.1109/SBAC-PADW.2015.13","DOIUrl":"https://doi.org/10.1109/SBAC-PADW.2015.13","url":null,"abstract":"This paper describes a novel speculation technique for the optimization, and simultaneous execution, of multiple alternative traces of hot code regions. This technique, called Speculative Trace Optimization (STO), enumerates, optimizes, and speculatively executes traces of hot loops. It requires hardware support that can be provided in a similar fashion as that available in Hardware Transactional Memory (HTM) systems. This paper discusses the necessary features to support STO, namely multi-versioning, lazy conflict resolution, eager conflict detection, and transaction synchronization. A review of existing HTM architectures - Intel TSX, IBM BG/Q, and IBM POWER8 - shows that none of them have all the features required to implement STO. However, this work demonstrates that STO can be implemented on top of existing HTM architectures through the addition of privatization and pause/resume code. The evaluation of a prototype STO implementation, on top of Intel TSX, using benchmarks from Parboil, Media Bench, and SPEC2006, indicates that STO can yield whole-program speedups of up to 9%. This initial result is promising given that the prototype has significant overhead caused by the code that compensates for TSX absent features. An analysis, included in the paper, suggests that HTM mechanisms have the potential to considerably improve trace performance provided that they efficiently implement the suggested features.","PeriodicalId":161685,"journal":{"name":"2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125149665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Many SVDs on GPU for Image Mosaic Assemble 基于GPU的图像拼接svd

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.22

I. Badolato, Luciano de Paula, R. Farias

引用次数: 2

Replicating the Performance Evaluation of an N-Body Application on a Manycore Accelerator 在多核加速器上复制n体应用程序的性能评估

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.17

V. G. Pinto, Vinicius Alves Herbstrith, L. Schnorr

引用次数: 2

Kanga: A Skeleton-Based Generic Interface for Parallel Programming Kanga:用于并行编程的基于骨架的通用接口

2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW) Pub Date : 2015-10-18 DOI: 10.1109/SBAC-PADW.2015.16

Deives Kist, Bruno Pinto, Rodrigo Bazo, A. R. D. Bois, G. H. Cavalheiro

引用次数: 5