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2009 5th Southern Conference on Programmable Logic (SPL)最新文献

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Hardware accelerated aerial image simulation by FPGA 基于FPGA的航空图像硬件加速仿真
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914916
Hani Jamleh, C. C. Chen
{"title":"Hardware accelerated aerial image simulation by FPGA","authors":"Hani Jamleh, C. C. Chen","doi":"10.1109/SPL.2009.4914916","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914916","url":null,"abstract":"This paper describes a hardware implementation of aerial image simulation in lithography using FPGA. However, such simulators are presently performed using mainly software-based techniques on dedicated computers. The Hopkins partially coherent imaging equation is decomposed numerically by using singular value decomposition (SVD). The data input is a function which is consisting of rectangles as Manhattan geometry mask. For the convolution of mask functions with arbitrary kernels, a table lookup technique is used. For each single point intensity computation, it needs computation in the number of rectangles within a bounded window and the approximation order of the optical system adopted. This computation is done by FPGA on the order of O(R) instead of O(A·R) which is the case in temporal machines. It is clearly shown how FPGA can be utilized efficiently to reduce the cost of computation.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware/Software co-design using artificial neural network and evolutionaryy computing 利用人工神经网络和进化计算进行软硬件协同设计
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914912
M. A. Dias, W. S. Lacerda
{"title":"Hardware/Software co-design using artificial neural network and evolutionaryy computing","authors":"M. A. Dias, W. S. Lacerda","doi":"10.1109/SPL.2009.4914912","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914912","url":null,"abstract":"Hardware/Software co-design is an important problem nowadays and is involved in many hardware research and development fields. Hardware/software partitioning problem is one of the most important questions on co-design that defines how parts of a hardware/software system should be implemented on which a fast and good solution is essential. This paper proposes a new way on hardware/software partitioning problem solving using an artificial neural network trained with resilient back propagation algorithm and feed-forward architecture.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128254712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Digital circuit evolution for scalability 可扩展性的数字电路进化
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914923
X. She
{"title":"Digital circuit evolution for scalability","authors":"X. She","doi":"10.1109/SPL.2009.4914923","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914923","url":null,"abstract":"Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolution algorithm. One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines evolvable hardware based on a 2-LUT (2-input lookup table) array, which allows the evolution of large circuits via decomposition. The proposed EHW has been tested with multipliers and logic circuits taken from the Microelectronics Centre of North Carolina (MCNC) benchmark library. The experimental results demonstrate that the proposed scheme improves the evolution of logic circuits in terms of the number of generations, area and delay, reduces computational time and enables the evolution of large circuits.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122045436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SCAR-FPGA : A novel side-channel attack resistant fpga SCAR-FPGA:一种新型的抗侧信道攻击fpga
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914903
Ali Mokari, B. Ghavami, H. Pedram
{"title":"SCAR-FPGA : A novel side-channel attack resistant fpga","authors":"Ali Mokari, B. Ghavami, H. Pedram","doi":"10.1109/SPL.2009.4914903","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914903","url":null,"abstract":"In design of embedded systems for security applications, flexibility and tamper-resistance are two important factors to be considered. High frequency of updates and high costs of ASIC and their long design time urge us to use a secure FPGA as an alternative. In this paper a secure FPGA is proposed for secure implementation of crypto devices. The FPGA architecture is based on Asynchronous methodology and is resistant against multiple side channel attacks such as Power Attacks and Fault Attacks. AES algorithm implementation shows the native resistance of SCAR-FPGA.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131953342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
PAM Map: An architecture-independent logic block mapping algorithm for SRAM-based FPGAs PAM映射:一种架构独立的逻辑块映射算法，用于基于sram的fpga
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914887
Yun Shao, Jinmei Lai, Jian Wang, J. Tong
{"title":"PAM Map: An architecture-independent logic block mapping algorithm for SRAM-based FPGAs","authors":"Yun Shao, Jinmei Lai, Jian Wang, J. Tong","doi":"10.1109/SPL.2009.4914887","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914887","url":null,"abstract":"In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmable logic blocks of arbitrary architectures. We formulate the problem as a graph matching problem and present an architecture-independent algorithm for this purpose. This algorithm also obtains a best area saving of 4% compared to architecture-dependent methods.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125268809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reconfigurable architecture for binary images invariant moment extraction 二值图像不变矩提取的可重构结构
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914924
Guilherme H. R. Jorge, V. O. Roda, J. Oliver, J. P. Acle, S. Fernandez
{"title":"Reconfigurable architecture for binary images invariant moment extraction","authors":"Guilherme H. R. Jorge, V. O. Roda, J. Oliver, J. P. Acle, S. Fernandez","doi":"10.1109/SPL.2009.4914924","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914924","url":null,"abstract":"Moments of the intensity function of a group of pixels have been used fo rthe representation and recognition of objects in two dimensional images. Due to the high computational cost of evaluating the moments, the search for faster computing architectures is very important. This work presents a soft core architecture for the extraction of invariant moments from binary images, using high density logic programmable devices.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125580969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mitigating and tolerating SEU effects in switch modules of SRAM-based FPGAs 在基于sram的fpga的交换模块中减轻和容忍SEU效应
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914902
Alireza Rohani, H. Zarandi
{"title":"Mitigating and tolerating SEU effects in switch modules of SRAM-based FPGAs","authors":"Alireza Rohani, H. Zarandi","doi":"10.1109/SPL.2009.4914902","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914902","url":null,"abstract":"This paper proposes three methods to mitigate and tolerate SEU-caused errors on the configuration bits of SRAM-based field programmable gate arrays. The proposed methods are based on error detection and correction codes which are able to detect or correct SEU-caused errors in Switch Modules. The effects of proposed methods on the various parameters such as area, delay and power consumption for ten ITC'99 benchmark circuits have been evaluated with synopsis® CAD tool and compared with previous work. The experimental results show that the proposed methods can detect or correct 100% single errors in Switch Modules by imposing area overhead between 2% and 60%, delay overhead between 25% and 100% and power consumption overhead between 1% and 25%.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"3 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132434141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A general Image Processing architecture for FPGA 用于FPGA的通用图像处理体系结构
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914921
F. Cappabianco, G. Araújo, R. Azevedo, A. Falcão
{"title":"A general Image Processing architecture for FPGA","authors":"F. Cappabianco, G. Araújo, R. Azevedo, A. Falcão","doi":"10.1109/SPL.2009.4914921","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914921","url":null,"abstract":"The Image Foresting Transform (IFT) is a general tool for the design of image processing operators based on dynamic programming. Silicon Image Forest Transform (SIFT) is a fast 8-bit data architecture for IFT-based operators in FPGA. It can implement queue-based methods such as morphological reconstructions, watershed transforms, shape saliences, distance transforms, skeletonization, edge tracking, with runtime gains from hundreds to thousands over the respective implementations in software. In this paper, we further extend the SIFT architecture to support 8- and 16-bit data and kernel-based operators such as dilation/erosion, smoothing, border enhancement, and sharpness filters. Moreover, we considerably improved the clock operation frequency and processing parallelism of SIFT.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132703199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fast radix 2K dividers for FPGAs 用于fpga的快速基数2K除法器
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914892
G. Sutter, J. Deschamps
{"title":"Fast radix 2K dividers for FPGAs","authors":"G. Sutter, J. Deschamps","doi":"10.1109/SPL.2009.4914892","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914892","url":null,"abstract":"In this paper we present radix r = 2k divider for fixed-point operands. The divider divides in a radix r = 2k, producing k bits at each iteration. The proposed digit recurrence algorithm has two different architectures, a first one for general hardware implementation, and the second one is optimized for configurable logic (FPGAs). Results show a speedup greater to three times respect to a classical non-restoring division implemented in Xilinx Devices. Additionally a throughput-latency-area comparison of pipelined and sequential dividers implementation is disclosed.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"14 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113962964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FuSE - a hardware accelerated HDL fault injection tool 一个硬件加速HDL故障注入工具
2009 5th Southern Conference on Programmable Logic (SPL) Pub Date : 2009-04-01 DOI: 10.1109/SPL.2009.4914906
M. Jeitler, M. Delvai, Stefan Reichor
{"title":"FuSE - a hardware accelerated HDL fault injection tool","authors":"M. Jeitler, M. Delvai, Stefan Reichor","doi":"10.1109/SPL.2009.4914906","DOIUrl":"https://doi.org/10.1109/SPL.2009.4914906","url":null,"abstract":"The ongoing miniaturization of digital circuits makes them more and more susceptible to faults which also complicates the design of fault tolerant systems. In this context fault injection plays an important role in the process of fault tolerance validation. As a result many fault injection tools have emerged during the last decade. However these tools only operate on specific domains and can therefore be referred to as hardware- or software-, simulation- or emulation based techniques. In this paper we present FuSE, a single fault injection tool which covers multiple domains as well as different fault injection purposes. FuSE has been designed for usage with the SEmulator® - an FPGA-based hardware accelerator. The created tool set has been fully automated for the fault injection process and only requires a VHDL description and a testbench of the circuit under test. FuSE can then perform fault injection experiments with a diagnostic resolution that is known from simulation-based approaches, but at a speed that even handles long running experiments with ease.","PeriodicalId":159669,"journal":{"name":"2009 5th Southern Conference on Programmable Logic (SPL)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123989476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
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