发布求助
文献互助 智能选刊 最新文献

2006 IEEE Design and Diagnostics of Electronic Circuits and systems最新文献

筛选
英文 中文
Normal Basis Multipliers of General Digit Width Applicable in ECC 通用位宽法基乘法器，适用于ECC
2006 IEEE Design and Diagnostics of Electronic Circuits and systems Pub Date : 2006-04-18 DOI: 10.1109/DDECS.2006.1649596
M. Novotný, Jan Schmidt
{"title":"Normal Basis Multipliers of General Digit Width Applicable in ECC","authors":"M. Novotný, Jan Schmidt","doi":"10.1109/DDECS.2006.1649596","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649596","url":null,"abstract":"We present two architectures of digit-serial normal basis multiplier over GF(2m). The multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in public-key cryptographic systems based on elliptic-curves, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131457508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SOC Diagnostic Design Using RESPIN Architecture SOC诊断设计使用RESPIN架构
2006 IEEE Design and Diagnostics of Electronic Circuits and systems Pub Date : 2006-04-18 DOI: 10.1109/DDECS.2006.1649626
Zbynek Mader, Michal Jarkovský
{"title":"SOC Diagnostic Design Using RESPIN Architecture","authors":"Zbynek Mader, Michal Jarkovský","doi":"10.1109/DDECS.2006.1649626","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649626","url":null,"abstract":"This paper describes realization of a project that is concerned with a diagnostic system of a SOC. The diagnostic system used RESPIN architecture is based on the IEEE 1500 standard and allows testing of cores by compressed test patterns. The patterns for certain core under test are decompressed in the scan chains of the other idle core during the test time. The compressed form of the test patterns is prepared by the algorithm COMPAS and stored in the memory of the SOC. The diagnostic system was implemented to the FPSLIC AT94K circuit that contain FPGA for cores, processor for control test procedure and the memory for storing the compressed test data in one system chip","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"9 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131943892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comprehensive design of a high frequency PLL synthesizer for ZigBee application ZigBee高频锁相环合成器的综合设计
2006 IEEE Design and Diagnostics of Electronic Circuits and systems Pub Date : 2006-04-18 DOI: 10.1109/DDECS.2006.1649567
A. Timár, Á. Vámos, G. Bognár
{"title":"Comprehensive design of a high frequency PLL synthesizer for ZigBee application","authors":"A. Timár, Á. Vámos, G. Bognár","doi":"10.1109/DDECS.2006.1649567","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649567","url":null,"abstract":"Time-to-market demands shorter design period of applied semiconductor devices. For this reason the iteration steps, the simulation time and repetitions have to be minimized along the design flow. In this paper a new design method of a phase locked loop (PLL) frequency synthesizer and its complete design flow is introduced. This synthesizer is designed mainly for ZigBee application. In this case the top-down design methodology was used. At higher hierarchy levels the Verilog-AMS hardware description language and various Matlab tools were applied. This analogue system will have to be realized on 0.35mum CMOS technology, so the complete layout has to be designed as well. The work has been focused on the main critical element of the PLL circuit, therefore two different types of a voltage controlled oscillator (VCO) blocks were realized. The carrier frequency is around 2.4 GHz during transmission according to the ZigBee standard, thus the VCOs were designed for operating on this frequency. In this paper, the mixed-signal simulation results of the entire system will be introduced, as well","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132917176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Self-refreshing Multiple Valued Memory 自刷新多值内存
2006 IEEE Design and Diagnostics of Electronic Circuits and systems Pub Date : 2006-04-18 DOI: 10.1109/DDECS.2006.1649584
J. Lomsdalen, R. Jensen, Y. Berg
{"title":"Self-refreshing Multiple Valued Memory","authors":"J. Lomsdalen, R. Jensen, Y. Berg","doi":"10.1109/DDECS.2006.1649584","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649584","url":null,"abstract":"This paper introduces a structure for self-refreshing multiple valued memory. The idea is to use structures having repeating patterns, to represent different saved values. Assuming a clocked repeating finite pattern, each pattern will repeat themselves after a finite number of clock pulses N, having N different phases. The values saved will be represented by both a pattern, and the phase of the pattern. The criterion for being self-refreshing is being fulfilled by resetting the pattern to a known value at least once every period. Some of these structures are quite possible to implement without a linear relation between the levels saved (radixes) and the number of transistors. This can make it competitive as memory for some certain multiple valued logic applications, being integrated between logic structures on chip","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133986178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A hybrid genetic algorithm for constrained hardware-software partitioning 约束软硬件分区的混合遗传算法
2006 IEEE Design and Diagnostics of Electronic Circuits and systems Pub Date : 1900-01-01 DOI: 10.1109/tridnt.2006.1649119
Pierre-André Mudry, G. Zufferey, G. Tempesti
{"title":"A hybrid genetic algorithm for constrained hardware-software partitioning","authors":"Pierre-André Mudry, G. Zufferey, G. Tempesti","doi":"10.1109/tridnt.2006.1649119","DOIUrl":"https://doi.org/10.1109/tridnt.2006.1649119","url":null,"abstract":"In this article, we propose a novel partitioning method for hardware-software codesign based on a genetic algorithm that has been enhanced for this specific task. Given a high-level program and an area constraint, our software considers different granularities levels to discover the most interesting blocks to be implemented in ad hoc functional units that can then be used as new instructions in a move processor. Various optimizations are conducted to obtain a clean, very fast (in the order of a few seconds) and efficient partitioning on programs ranging from a few to several hundreds of lines of code.","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127005181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信