Journal of Electrical Engineering-elektrotechnicky Casopis最新文献

Design of a battery charging system fed by thermoelectric generator panels using MPPT techniques 基于MPPT技术的热电发电板电池充电系统设计

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0043

Mustafa F. Mohammed, Mohammed A. Qasim

引用次数: 0

Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider 面积和功率效率除以32/33双模预标器，使用分频器AVLS的分频路径TSPC

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0048

Premananda Belegehalli Siddaiah, Sahithi Narsepalli, Sanya Mittal, Abdur Rehman

{"title":"Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider","authors":"Premananda Belegehalli Siddaiah, Sahithi Narsepalli, Sanya Mittal, Abdur Rehman","doi":"10.2478/jee-2023-0048","DOIUrl":"https://doi.org/10.2478/jee-2023-0048","url":null,"abstract":"Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Precision of sinewave amplitude estimation in the presence of additive noise and quantization error 存在加性噪声和量化误差时正弦波振幅估计的精度

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0045

Francisco André Corrêa Alegria

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Elementary design and analysis of QCA-based T-flipflop for nanocomputing 纳米计算中基于qca的t触发器的初步设计与分析

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0041

Angshuman Khan

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Model-free predictive current control of Syn-RM based on time delay estimation approach 基于时延估计的Syn-RM无模型预测电流控制

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0042

Mohamed Essalih Boussouar, Abdelghani Chelihi, Khaled Yahia, Antonio J. Marques Cardoso

{"title":"Model-free predictive current control of Syn-RM based on time delay estimation approach","authors":"Mohamed Essalih Boussouar, Abdelghani Chelihi, Khaled Yahia, Antonio J. Marques Cardoso","doi":"10.2478/jee-2023-0042","DOIUrl":"https://doi.org/10.2478/jee-2023-0042","url":null,"abstract":"Abstract This paper investigates an optimal model-free control design for a synchronous reluctance motor (Syn-RM) with unknown nonlinear dynamic functions, parameter variations, and disturbances. The idea is to combine a predictive control with a time-delay estimation technique (TDE) in order to successfully deal with the system’s uncertainties and make the Syn-RM control scheme easy to implement in real-time. This model-free control strategy comprises two cascade control loops namely outer and inner loops. The outer loop is designed for the mechanical part of Syn-RM to ensure the convergence of the speed dynamics by using a proportional-integral controller while the inner loop is developed to control the uncertain dynamics of currents via an optimal robust controller. In the proposed current loop, the predictive control is enhanced by the inclusion of ultra-local model theory where dynamic functions and disturbances are estimated by instantaneous input-output measurements of the Syn-RM using the TDE approach. Moreover, a particle swarm optimization (PSO) algorithm is also proposed to find the optimal design parameters to improve the dynamic performances of the closed-loop control system. Numerical validation tests of the proposed TDE-based model-free predictive current control (TDE-MFPCC) method are performed in the simulation environment of the Syn-RM system, and the results show the robustness and the effectiveness of the proposed TDE-MFPCC compared to the conventional model-based PCC.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Design of wide-band high-linearity transimpedance amplifier using standard CMOS technology 采用标准CMOS技术设计宽带高线性跨阻放大器

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0049

Zheng Gu, Siqi Wang, Chungang Lu, Lei Song, Zhenghao Lu, Yonghua Chu, Xiaopeng Yu

引用次数: 0

Performance analysis of speech enhancement using spectral gating with U-Net U-Net频谱门控语音增强性能分析

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0044

Jharna Agrawal, Manish Gupta, Hitendra Garg

{"title":"Performance analysis of speech enhancement using spectral gating with U-Net","authors":"Jharna Agrawal, Manish Gupta, Hitendra Garg","doi":"10.2478/jee-2023-0044","DOIUrl":"https://doi.org/10.2478/jee-2023-0044","url":null,"abstract":"Abstract Many speech processing systems’ crucial frontends include speech enhancement. Single-channel speech enhancement experiences a number of technological challenges. Due to the advent of cloud-based technology and the use of deep learning systems in big data, deep neural networks in particular have recently been seen as a potent means for complex classification and regression. In this work, spectral gating noise filter is combined with deep neural network U-Net to enhance the performance of speech enhancement network. Further, for performance analysis three distinct objective functions namely, Mean Square Error, Huber Loss and Mean Absolute Error are considered as loss functions. In addition, comparison of three different optimizers Adam, Adagrad and Stochastic Gradient Descent is presented. Proposed system is tested and evaluated on LibriSpeech and NOIZEUS datasets and compared to other state-of-the-art systems. It demonstrates that, in comparison to other state-of-the-art models, the proposed network outperformed them with PESQ scores of 2.737420 for training and 2.67857 for testing, along with better generalization ability.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal-magnetic performance analysis for smart fluid dampers 智能流体阻尼器的热磁性能分析

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0046

Antonino Caracciolo, Samuele Ollio, Alessio Pizzi, Leonardo Romeo, Antonio Enrico Serranò, Giuseppe Vasily Tringali, Antonino Greco, Mario Versaci

{"title":"Thermal-magnetic performance analysis for smart fluid dampers","authors":"Antonino Caracciolo, Samuele Ollio, Alessio Pizzi, Leonardo Romeo, Antonio Enrico Serranò, Giuseppe Vasily Tringali, Antonino Greco, Mario Versaci","doi":"10.2478/jee-2023-0046","DOIUrl":"https://doi.org/10.2478/jee-2023-0046","url":null,"abstract":"Abstract Over the years, the Italian Government has taken significant strides in promoting road safety awareness among the students in high schools to create an awareness of prevention and a consciousness of road safety in the student population. In this context, an agreement was signed between the DICEAM Department of the “Mediterranea” University of Reggio Calabria (Italy) and the “Euclide” Higher Education Institute Bova Marina (Italy) to combine road safety with research science in the Science, Technology, Engineering, and Mathematics (STEM) area. With the primary aim of “knowing in order to act”, the students focused on the multi-physics design of magnetorheological fluid dampers as high-performance devices (simple to design and requiring reduced maintenance) for vehicle suspensions, especially class B vehicles. By combining road safety considerations with multi-physics scientific disciplines, the project seeks to emphasize the importance of prevention and knowledge-based action. The study explores the use of magnetorheological fluid dampers, powered by electric current and magnetic induction distribution with thermal loads, to provide appropriate yield stress for developing damping action with repercussions on the quality of road safety. The paper delves into the basic principles of FEM (Finite Element Method) techniques for analyzing an MR damper from both magnetostatic (the main cause generating the damping effect) and thermal perspectives (thermal effects are strongly influenced by environmental conditions). The analysis of an asymmetrical device, where the damping action relies on an MR fluid strip, reveals the significant influence of magnetic and thermal stresses on the magnetization of individual particles and the overall viscosity of the MR fluid.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Methods of computer modeling of electromagnetic field propagation in urban scenarios for Internet of Things 城市物联网场景下电磁场传播的计算机建模方法

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0050

Anatolii Kliuchka, René Harťanský, Ján Halgoš

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Realization of a memcapacitance emulator utilizing a singular current-mode active block 利用单一电流模有源块实现记忆电容仿真器

4区工程技术

Journal of Electrical Engineering-elektrotechnicky Casopis Pub Date : 2023-10-01 DOI: 10.2478/jee-2023-0047

Mihajlo Tatović, Predrag B. Petrović

{"title":"Realization of a memcapacitance emulator utilizing a singular current-mode active block","authors":"Mihajlo Tatović, Predrag B. Petrović","doi":"10.2478/jee-2023-0047","DOIUrl":"https://doi.org/10.2478/jee-2023-0047","url":null,"abstract":"Abstract This paper introduces a novel circuit design for a memcapacitance emulator, employing a single Voltage Differencing Current Conveyor (VDCC) as its core element. The emulator circuit has been intricately designed, employing only capacitors as grounded passive components. One remarkable aspect of these circuits is their inherent electronic tunability, allowing for precise control of the achieved inverse memcapacitance. The theoretical analysis of the emulator includes a comprehensive examination of potential non-idealities and parasitic influences. Careful selection of passive circuit elements has been made to minimize the impact of these undesirable effects. In contrast to extant designs cataloged in the existing literature, the presented circuitry manifests remarkable simplicity in its configuration. Furthermore, it exhibits a wide operational frequency range, extending up to 50MHz, and effectively clears the non-volatility criterion. To substantiate the efficacy of the devised circuits, comprehensive LTSpice simulations have been conducted, employing a 0.18 μm TSMC process parameter and a power supply of ±0.9 V. These simulations provide robust evidence of the emulator’s performance, reaffirming the feasibility and practicality of the proposed approach in the domain of memcapacitance emulation.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0