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A Cost-Effective FPGA-based Fault Simulation Environment 基于fpga的低成本故障仿真环境
2011 Workshop on Fault Diagnosis and Tolerance in Cryptography Pub Date : 2011-09-29 DOI: 10.1109/FDTC.2011.19
Angelika Janning, Johann Heyszl, F. Stumpf, G. Sigl
{"title":"A Cost-Effective FPGA-based Fault Simulation Environment","authors":"Angelika Janning, Johann Heyszl, F. Stumpf, G. Sigl","doi":"10.1109/FDTC.2011.19","DOIUrl":"https://doi.org/10.1109/FDTC.2011.19","url":null,"abstract":"In this contribution, we present an FPGA-based simulation environment for fault attacks on cryptographic hardware designs. With our methodology, we are able to simulate the effects of global fault attacks from e.g., spikes and local attacks from e.g., focused laser beams. The environment simulates transient bit-flip faults in sequential elements of a digital design. In this way it is tailored to the simulation of fault attacks on cryptographic designs. It is a tool to verify the design's behaviour in case of fault attacks and to verify implemented countermeasures. The environment is script-based for fully automated modification of the digital design and simulation. It can handle designs in VHDL as well as in Verilog language and does not require modifications to the design's source code. We used our environment in a case study and successfully tested the effectiveness of a fault detection countermeasure in an elliptic curve cryptography design.","PeriodicalId":150423,"journal":{"name":"2011 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129177263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Local and Direct EM Injection of Power Into CMOS Integrated Circuits 局部和直接电磁注入功率到CMOS集成电路
2011 Workshop on Fault Diagnosis and Tolerance in Cryptography Pub Date : 2011-09-29 DOI: 10.1109/FDTC.2011.18
F. Poucheret, Karim Tobich, M. Lisart, L. Chusseau, B. Robisson, P. Maurine
{"title":"Local and Direct EM Injection of Power Into CMOS Integrated Circuits","authors":"F. Poucheret, Karim Tobich, M. Lisart, L. Chusseau, B. Robisson, P. Maurine","doi":"10.1109/FDTC.2011.18","DOIUrl":"https://doi.org/10.1109/FDTC.2011.18","url":null,"abstract":"The paper aims at demonstrating experimentally that the tiny Electro Magnetic (EM) coupling between the tip end of a micro-antenna is sufficient to locally and directly inject power into CMOS Integrated Circuits (IC). More precisely, experimental results show that such electrical couplings are sufficient to disturb, with and without removing the IC package, the behavior of 90nm CMOS Ring Oscillators, a representative structure of CMOS logic but also a constituting element of some True Random Number Generators (TRNGs) or clock generator.","PeriodicalId":150423,"journal":{"name":"2011 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132979397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
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