13th Symposium on High Performance Interconnects (HOTI'05)最新文献

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.34

J. Turner

{"title":"Using the open network lab","authors":"J. Turner","doi":"10.1109/CONECT.2005.34","DOIUrl":"https://doi.org/10.1109/CONECT.2005.34","url":null,"abstract":"The Open Network Laboratory is a resource designed to enable experimental evaluation of advanced networking concepts in a realistic operating environment. The laboratory is built around a set of open-source, extensible, high performance routers, which can be accessed by remote users through a remote laboratory interface (RLI). The RLI allows users to configure the testbed network, run applications and monitor those running applications using built-in data gathering mechanisms. Support for data visualization and real-time remote display is provided. The RLI also allows users to extend, modify or replace the software running in the routers' embedded processors and to similarly extend, modify or replace the routers' packet processing hardware, which is implemented largely using field programmable gate arrays. The routers included in the testbed are architecturally similar to high performance commercial routers, enabling researchers to evaluate their ideas in a much more realistic context than can be provided by PC-based routers. The Open Network Laboratory is designed to provide a setting in which systems researchers can evaluate and refine their ideas and then demonstrate them to those interested in moving their technology into new products and services. This tutorial will teach users how to use the ONL. It will include detailed presentations on the system architecture and principles of operation, as well as live demonstrations. We also plan to give participants an opportunity for hands-on experience with setting up and running experiments themselves.","PeriodicalId":148282,"journal":{"name":"13th Symposium on High Performance Interconnects (HOTI'05)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127965528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Breaking the connection: RDMA deconstructed 断开连接:解构RDMA

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.9

Rajeev Sivaram, R. Govindaraju, P. Hochschild, Robert Blackmore, Piyush Chaudhary

引用次数: 12

High-speed and low-power network search engine using adaptive block-selection scheme 高速低功耗网络搜索引擎采用自适应块选择方案

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.20

M. Akhbarizadeh, M. Nourani, R. Panigrahy, Samar Sharma

引用次数: 6

Design of randomized multichannel packet storage for high performance routers 高性能路由器随机多通道分组存储设计

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.17

S. Sushanth Kumar, P. Crowley, J. Turner

{"title":"Design of randomized multichannel packet storage for high performance routers","authors":"S. Sushanth Kumar, P. Crowley, J. Turner","doi":"10.1109/CONECT.2005.17","DOIUrl":"https://doi.org/10.1109/CONECT.2005.17","url":null,"abstract":"High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity to provide the required storage economically. The memory bandwidth required for packet storage subsystems often exceeds the bandwidth of individual memory devices, making it necessary to implement packet storage using multiple memory channels. This raises the question of how to design multichannel storage systems that make effective use of the available memory and memory bandwidth, while forwarding packets at link rate in the presence of arbitrary packet retrieval patterns. A recent series of papers has demonstrated an architecture that uses on-chip SRAM to buffer packets going to/from a multichannel storage system, while maintaining high performance in the presence worst-case traffic patterns. Unfortunately, the amount of on-chip storage required grows as the product of the number of channels and the number of separate queues served by the packet storage system. This makes it too expensive to use in systems with large numbers of queues. We show how to design a practical randomized packet storage system that can sustain high performance using an amount of on-chip storage that is independent of the number of queues.","PeriodicalId":148282,"journal":{"name":"13th Symposium on High Performance Interconnects (HOTI'05)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115857829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

A scalable, self-routed, terabit capacity, photonic interconnection network 一个可扩展的，自路由的，太比特容量的，光子互连网络

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.6

A. Shacham, Benjamin G. Lee, K. Bergman

引用次数: 19

Reconfigurable networking hardware: a classroom tool 可重构网络硬件:课堂工具

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.32

M. Casado, G. Watson, N. McKeown

引用次数: 13

A scalable switch for service guarantees 可扩展的交换机，提供服务保证

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.5

Bill Lin, I. Keslassy

引用次数: 10

Performance characterization of a 10-Gigabit Ethernet TOE 10千兆以太网TOE的性能表征

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.30

Wu-chun Feng, P. Balaji, C. Baron, L. Bhuyan, D. Panda

{"title":"Performance characterization of a 10-Gigabit Ethernet TOE","authors":"Wu-chun Feng, P. Balaji, C. Baron, L. Bhuyan, D. Panda","doi":"10.1109/CONECT.2005.30","DOIUrl":"https://doi.org/10.1109/CONECT.2005.30","url":null,"abstract":"Though traditional Ethernet based network architectures such as Gigabit Ethernet have suffered from a huge performance difference as compared to other high performance networks (e.g, InfiniBand, Quadrics, Myrinet), Ethernet has continued to be the most widely used network architecture today. This trend is mainly attributed to the low cost of the network components and their backward compatibility with the existing Ethernet infrastructure. With the advent of 10-Gigabit Ethernet and TCP offload engines (TOEs), whether this performance gap be bridged is an open question. In this paper, we present a detailed performance evaluation of the Chelsio T110 10-Gigabit Ethernet adapter with TOE. We have done performance evaluations in three broad categories: (i) detailed micro-benchmark performance evaluation at the sockets layer, (ii) performance evaluation of the message passing interface (MPI) stack atop the sockets interface, and (iii) application-level evaluations using the Apache Web server. Our experimental results demonstrate latency as low as 8.9 /spl mu/s and throughput of nearly 7.6 Gbps for these adapters. Further, we see an order-of-magnitude improvement in the performance of the Apache Web server while utilizing the TOE as compared to the basic 10-Gigabit Ethernet adapter without TOE.","PeriodicalId":148282,"journal":{"name":"13th Symposium on High Performance Interconnects (HOTI'05)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134359794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 94

Hybrid cache architecture for high speed packet processing 用于高速分组处理的混合缓存体系结构

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1049/iet-cdt:20060085

Z. Liu, K. Zheng, B. Liu

引用次数: 7

Can memory-less network adapters benefit next-generation infiniband systems? 无内存网络适配器能使下一代无限带宽系统受益吗?

13th Symposium on High Performance Interconnects (HOTI'05) Pub Date : 2005-08-17 DOI: 10.1109/CONECT.2005.10

S. Sur, Abhinav Vishnu, Hyun-Wook Jin, Wei Huang, D. Panda

{"title":"Can memory-less network adapters benefit next-generation infiniband systems?","authors":"S. Sur, Abhinav Vishnu, Hyun-Wook Jin, Wei Huang, D. Panda","doi":"10.1109/CONECT.2005.10","DOIUrl":"https://doi.org/10.1109/CONECT.2005.10","url":null,"abstract":"InfiniBand is emerging as a high-performance interconnect. It is gaining popularity because of its high performance and open standard. Recently, PCI-Express, which is the third generation high-performance I/O bus used to interconnect peripheral devices, has been released. The third generation of InfiniBand adapters allow applications to take advantage of PCI-Express. PCI-Express offers very low latency access of the host memory by network interface cards (NICs). Earlier generation InfiniBand adapters used to have an external DIMM attached as local NIC memory. This memory was used to store internal information. This memory increases the overall cost of the NIC. In this paper we design experiments, analyze the performance of various communication patterns and end applications on PCI-Express based systems, whose adapters can be chosen to run with or without local NIC memory. Our investigations reveal that on these systems, the memory fetch latency is the same for both local NIC memory and host memory. Under heavy I/O bus usage, the latency of a scatter operation increased only by 10% and only for message sizes IB -4 KB. These memory-less adapters allow more efficient use of overall system memory and show practically no performance impact (less than 0.1%) for the NAS parallel benchmarks on 8 processes. These results indicate that memory-less network adapters can benefit next generation InfiniBand systems.","PeriodicalId":148282,"journal":{"name":"13th Symposium on High Performance Interconnects (HOTI'05)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129772697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18