2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)最新文献

DESIV: Differential Fault Analysis of SIV-Rijndael256 with a Single Fault 单故障SIV-Rijndael256的微分故障分析

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300267

Aikata, Banashri Karmakar, Dhiman Saha

{"title":"DESIV: Differential Fault Analysis of SIV-Rijndael256 with a Single Fault","authors":"Aikata, Banashri Karmakar, Dhiman Saha","doi":"10.1109/HOST45689.2020.9300267","DOIUrl":"https://doi.org/10.1109/HOST45689.2020.9300267","url":null,"abstract":"This work analyzes the strength of NIST Lightweight Cryptography (LWC) Round 1 Candidate SIV-Rijndael256 in light of Differential Fault Attacks (DFA). It is observed that SIV-Rijndael256 presents an interesting case for DFA due to its large state-size which has been capitalized in this work to contribute to the state-of-the-art in DFA on AES-like ciphers. We first study the differential properties over three rounds of the cipher and then use it to mount a DFA that uses a classical strategy in conjunction with the properties of the key-schedule. The nonce-misuse property of SIV-Rijndael256 facilitates the use of DFA and is exploited to reduce the key-space from 2128 to just one using only a single random byte fault in the internal state. Moreover, the support for the release of unverified plaintexts which have been shown in literature as a vulnerability to DFA, makes the decryption also vulnerable to the same attack. Finally, the ability to uniquely retrieve the key using just a single fault makes the attack, reported here, an optimal DFA. To the best of our knowledge, this is the first differential fault analysis of any candidate in the NIST LWC competition.","PeriodicalId":147386,"journal":{"name":"2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116298069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist ReGDS:从GDSII到门级网表的逆向工程框架

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300272

Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, D. Pan

{"title":"ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist","authors":"Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, D. Pan","doi":"10.1109/HOST45689.2020.9300272","DOIUrl":"https://doi.org/10.1109/HOST45689.2020.9300272","url":null,"abstract":"With many fabless companies outsourcing integrated circuit (IC) fabrication, the extent of design information recoverable by any third-party foundry remains clouded. While traditional reverse engineering schemes from the layout employ expensive high-resolution imaging techniques to recover design information, the extent of design information that can be recovered by the foundry remains ambiguous. To address this ambiguity, we propose ReGDS, a layout reverse engineering (RE) framework, posing as an inside-foundry attack to acquire original design intent. Our framework uses the layout, in GDSII format, and the technology library to extract the transistor-level connectivity information, and exploits unique relationship-based matching to identify logic gates and thereby, recover the original gate-level netlist. Employing circuits ranging from few hundreds to millions of transistors, we validate the scalability of our framework and demonstrate 100% recovery of the original design from the layout. To further validate the effectiveness of the framework in the presence of obfuscation schemes, we apply ReGDS to layouts of conventional XOR/MUX locked circuits and successfully recover the obfuscated netlist. By applying the Boolean SATisfiability (SAT) attack on the recovered obfuscated netlist, one can recover the entire key and, thereby, retrieve the original design intent. Thus ReGDS results in accelerated acquisition of the gate-level netlist by the attacker, in comparison to imaging-based RE schemes. Our experiments unearth the potential threat of possible intellectual property (IP) piracy at any third-party foundry.","PeriodicalId":147386,"journal":{"name":"2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132056788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A Post-Quantum Secure Discrete Gaussian Noise Sampler 后量子安全离散高斯噪声采样器

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300275

R. Agrawal, Lake Bu, M. Kinsy

{"title":"A Post-Quantum Secure Discrete Gaussian Noise Sampler","authors":"R. Agrawal, Lake Bu, M. Kinsy","doi":"10.1109/HOST45689.2020.9300275","DOIUrl":"https://doi.org/10.1109/HOST45689.2020.9300275","url":null,"abstract":"While the notion of achieving “quantum supremacy” may be debatable, rapid developments in the field of quantum computing are heading towards more realistic quantum computers. As practical quantum computers start becoming more feasible, the requirement to have quantum secure cryptosystems becomes more compelling. Due to its many advantages, lattice based cryptography has become one of the key candidates for designing secure systems for the post-quantum era. The security of lattice-based cryptography is governed by the small error samples generated from a Gaussian distribution. Hence, the Gaussian distribution lies at the core of these cryptosystems. In this paper, we present the hardware design implementation of three different sampling algorithms including rejection, Box-Muller, and the Ziggurat method for the Gaussian Sampler. Our goal is to provide concrete recommendations for future use and adoption in various cryptosystems based on sampling efficiency, hardware cost and throughput. The key feature of our design implementation is that it performs high-precision sampling to meet the NIST’s recommended security level of 112-bits or higher for the postquantum era, which most existing hardware implementations fail to do. Furthermore, our design implementation is highly optimized for FPGA-based implementation and is also generic so that it can be seamlessly integrated into most cryptosystems. Synthesis results are obtained using Vivado design suite for a Xilinx Zynq-7010 CLG400ACX1341 FPGA board.","PeriodicalId":147386,"journal":{"name":"2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130553840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

LAHEL: Lightweight Attestation Hardening Embedded Devices using Macrocells LAHEL:使用Macrocells的轻量级认证加固嵌入式设备

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300257

Orlando Arias, Dean Sullivan, Haoqi Shan, Yier Jin

{"title":"LAHEL: Lightweight Attestation Hardening Embedded Devices using Macrocells","authors":"Orlando Arias, Dean Sullivan, Haoqi Shan, Yier Jin","doi":"10.1109/HOST45689.2020.9300257","DOIUrl":"https://doi.org/10.1109/HOST45689.2020.9300257","url":null,"abstract":"In recent years, we have seen an advent in software attestation defenses targeting embedded systems which aim to detect tampering with a device’s running program. With a persistent threat of an increasingly powerful attacker with physical access to the device, attestation approaches have become more rooted into the device’s hardware with some approaches even changing the underlying microarchitecture. These drastic changes to the hardware make the proposed defenses hard to apply to new systems. In this paper, we present and evaluate LAHEL as the means to study the implementation and pitfalls of a hardware-based attestation mechanism. We limit LAHEL to utilize existing technologies without demanding any hardware changes. We implement LAHEL as a hardware IP core which interfaces with the CoreSight Debug Architecture available in modern ARM cores. We show how LAHEL can be integrated to system on chip designs allowing for microcontroller vendors to easily add our defense into their products. We present and test our prototype on a Zynq-7000 SoC, evaluating the security of LAHEL against powerful time-of-check-time-of-use (TOCTOU) attacks, while demonstrating improved performance over existing attestation schemes.","PeriodicalId":147386,"journal":{"name":"2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131895957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Novel Golden-Chip-Free Clustering Technique Using Backscattering Side Channel for Hardware Trojan Detection 一种基于后向散射侧信道的无金芯片聚类技术用于硬件木马检测

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300127

Luong N. Nguyen, B. Yilmaz, Milos Prvulović

{"title":"A Novel Golden-Chip-Free Clustering Technique Using Backscattering Side Channel for Hardware Trojan Detection","authors":"Luong N. Nguyen, B. Yilmaz, Milos Prvulović","doi":"10.1109/HOST45689.2020.9300127","DOIUrl":"https://doi.org/10.1109/HOST45689.2020.9300127","url":null,"abstract":"Over the past few years, malicious hardware modifications, a.k.a. hardware Trojans (HT), have emerged as a major security threat because integrated circuit (IC) companies have been fabricating chips at offshore foundries due to various factors including time-to-market, cost reduction demands, and the increased complexity of ICs. Among proposed hardware Trojan detection techniques, reverse engineering appears to be the most accurate and reliable one because it works for all circuits and Trojan types without a golden example of the chip. However, because reverse engineering is an extremely expensive, time-consuming, and destructive process, it is difficult to apply this technique for a large population of ICs in a real test environment. This paper proposes a novel golden-chip-free clustering method using backscattering side-channel to divide ICs into groups of Trojan-free and Trojan-infected boards. The technique requires no golden chip or a priori knowledge of the chip circuitry, and divides a large population of ICs into clusters based on how HTs (if existed) affect their backscattered signals. This significantly reduces the size of test vectors for reverse engineering based detection techniques, thus enables deployment of reverse engineering approaches to a large population of ICs in a real testing scenario. The results are collected on 100 different FPGA boards where boards are randomly chosen to be infected or not. The results show that we can cluster the boards with 100% accuracy and demonstrate that our technique can tolerate manufacturing variations among hardware instances to cluster all the boards accurately for 9 different dormant Trojan designs on 3 different benchmark circuits from Trusthub. We have also shown that we can detect dormant Trojan designs whose trigger size has shrunk to as small as 0.19% of the original circuit with 100% accuracy as well.","PeriodicalId":147386,"journal":{"name":"2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122557417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Template Attacks against ECC: practical implementation against Curve25519 针对ECC的模板攻击:针对Curve25519的实际实现

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300261

Antoine Loiseau, Maxime Lecomte, J. Fournier

引用次数: 3

[Front matter] (前页)

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/host45689.2020.9300269

引用次数: 0

DeepEM: Deep Neural Networks Model Recovery through EM Side-Channel Information Leakage DeepEM: EM侧信道信息泄漏的深度神经网络模型恢复

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300274

Honggang Yu, Haocheng Ma, Kaichen Yang, Yiqiang Zhao, Yier Jin

{"title":"DeepEM: Deep Neural Networks Model Recovery through EM Side-Channel Information Leakage","authors":"Honggang Yu, Haocheng Ma, Kaichen Yang, Yiqiang Zhao, Yier Jin","doi":"10.1109/HOST45689.2020.9300274","DOIUrl":"https://doi.org/10.1109/HOST45689.2020.9300274","url":null,"abstract":"Neural Network (NN) accelerators are currently widely deployed in various security-crucial scenarios, including image recognition, natural language processing and autonomous vehicles. Due to economic and privacy concerns, the hardware implementations of structures and designs inside NN accelerators are usually inaccessible to the public. However, these accelerators still tend to leak crucial information through Electromagnetic (EM) side channels in addition to timing and power information. In this paper, we propose an effective and efficient model stealing attack against current popular large-scale NN accelerators deployed on hardware platforms through side-channel information. Specifically, the proposed attack approach contains two stages: 1) Inferring the underlying network architecture through EM sidechannel information; 2) Estimating the parameters, especially the weights, through a margin-based, adversarial active learning method. The experimental results show that the proposed attack approach can accurately recover the large-scale NN through EM side-channel information leakages. Overall, our attack highlights the importance of masking EM traces for large-scale NN accelerators in real-world applications.","PeriodicalId":147386,"journal":{"name":"2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128240888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 68

Bit2RNG: Leveraging Bad-page Initialized Table with Bit-error Insertion for True Random Number Generation in Commodity Flash Memory Bit2RNG:利用带有错误插入的坏页初始化表在商品闪存中生成真随机数

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300293

Wei Yan, Huifeng Zhu, Zhiyuan Yu, Fatemeh Tehranipoor, J. Chandy, Ning Zhang, Xuan Zhang

{"title":"Bit2RNG: Leveraging Bad-page Initialized Table with Bit-error Insertion for True Random Number Generation in Commodity Flash Memory","authors":"Wei Yan, Huifeng Zhu, Zhiyuan Yu, Fatemeh Tehranipoor, J. Chandy, Ning Zhang, Xuan Zhang","doi":"10.1109/HOST45689.2020.9300293","DOIUrl":"https://doi.org/10.1109/HOST45689.2020.9300293","url":null,"abstract":"Nowadays NAND flash memory is the de-facto storage technology that is widely used from compact commercial off-the-shelf (COTS) embedded devices to large-scale cloud computing facilities. Motivated by the growing demand for mobile and Internet-of-Thing (IoT) applications, researchers have proposed many innovative ways to leverage the physical characteristics of memory devices for different security functionalities. However, many existing solutions lack thorough considerations of practical factors such as device aging, implementation cost, and runtime speed, preventing them from being directly adopted for real-world industrial applications. In this work, we present a novel true random number generation method called $Bit^{2}RNG$ that leverages the intrinsic system resources by combining the bad pages and bit errors in NAND flash as a random source. Our solution requires no hardware modifications to the memory chip, its communication interface, or the flash controller, and consumes no additional system memory space. To demonstrate the capability and benefit of the proposed $Bit^{2}RNG$ technology, we explore several lightweight IoT applications including cryptographic key generation, device identification, and data provenance. The experimental results indicate that $Bit^{2}RNG$ is a practical solution with better system performance trade-off compared with other state-of-the-art TRNG techniques.","PeriodicalId":147386,"journal":{"name":"2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130585258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Evaluating Security Specification Mining for a CISC Architecture 评估CISC体系结构的安全规范挖掘

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2020-12-07 DOI: 10.1109/HOST45689.2020.9300291

Calvin Deutschbein, C. Sturton

{"title":"Evaluating Security Specification Mining for a CISC Architecture","authors":"Calvin Deutschbein, C. Sturton","doi":"10.1109/HOST45689.2020.9300291","DOIUrl":"https://doi.org/10.1109/HOST45689.2020.9300291","url":null,"abstract":"Security specification mining is a relatively new line of research that aims to develop a set of security properties for use during the design validation phase of the hardware life-cycle. Prior work in this field has targeted open-source RISC architectures and relies on access to the register transfer level design, developers’ repositories, bug tracker databases, and email archives. We develop Astarte, a tool for security specification mining of closed source, CISC architectures. As with prior work, we target properties written at the instruction set architecture (ISA) level. We use a full-system fast emulator with a lightweight extension to generate trace data, and we partition the space of security properties on security-critical signals in the architecture to manage complexity. We evaluate the approach for the x86-64 ISA. The Astarte framework produces roughly 1300 properties. Our automated approach produces a categorization that aligns with prior manual efforts. We study two known security flaws in shipped x86/x86-64 processor implementations and show that our set of properties could have revealed the flaws. Our analysis provides insight into those properties that are guaranteed by the ISA, those that are required of the operating system, and those that have become de facto properties by virtue of many operating systems assuming the behavior.","PeriodicalId":147386,"journal":{"name":"2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133108601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5