Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems最新文献

Error correcting codes for crosstalk effect minimization [system buses] 最小化串扰效应的纠错码[系统总线]

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-12-08 DOI: 10.1109/DFTVS.2003.1250120

Daniele Rossi, S. Cavallotti, C. Metra

引用次数: 4

Thermal management of high performance microprocessors in burn-in environment 高性能微处理器在老化环境下的热管理

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-12-08 DOI: 10.1109/DFTVS.2003.1250126

A. Vassighi, O. Semenov, M. Sachdev, A. Keshavarzi

引用次数: 10

Control constrained resource partitioning for complex SoCs [intra-chip wireless interconnects] 复杂soc的控制约束资源划分[片内无线互连]

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-12-08 DOI: 10.1109/DFTVS.2003.1250140

Dan Zhao, S. Upadhyaya, M. Margala

引用次数: 2

Quadruple time redundancy adders [error correcting adder] 四倍时间冗余加法器[纠错加法器]

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-12-08 DOI: 10.1109/DFTVS.2003.1250119

W. J. Townsend, J. Abraham, E. Swartzlander

引用次数: 27

Exploiting instruction redundancy for transient fault tolerance [microprocessor applications] 利用指令冗余进行瞬态容错[微处理器应用]

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-12-08 DOI: 10.1109/DFTVS.2003.1250154

Toshinori Sato

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引用次数: 3

An efficient functional test for the massively-parallel C/spl middot/RAM logic-enhanced memory architecture 大规模并行C/spl中点/RAM逻辑增强存储器结构的高效功能测试

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-11-03 DOI: 10.1109/DFTVS.2003.1250146

Xiaoling Sun, B. Cockburn, D. Elliott

引用次数: 1

Yield analysis of compiler-based arrays of embedded SRAMs 基于编译器的嵌入式ram阵列的良率分析

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-11-03 DOI: 10.1109/DFTVS.2003.1250089

Xiaopeng Wang, M. Ottavi, F. Lombardi

引用次数: 9

Analysis and testing of analog and mixed-signal circuits by an operation-region model: a case study of application and implementation 用操作区域模型分析和测试模拟和混合信号电路:应用和实现的案例研究

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-11-03 DOI: 10.1109/DFTVS.2003.1250122

Y. Miura, D. Kato

引用次数: 8

Multiple scan chain design technique for power reduction during test application in BIST 多扫描链设计技术在北京理工大学测试中的应用

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-11-03 DOI: 10.1109/DFTVS.2003.1250112

D. Ghosh, S. Bhunia, K. Roy

引用次数: 20

Clock calibration faults and their impact on quality of high performance microprocessors 时钟校准故障及其对高性能微处理器质量的影响

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2003-11-03 DOI: 10.1109/DFTVS.2003.1250096

C. Metra, T. M. Mak, Daniele Rossi

引用次数: 15