Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)最新文献_第5页

Comprehensive operating system for highly parallel machine 高度并行机的综合操作系统

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367135

N. Saito, H. Tokuda, T. Hagino, S. Oikawa, A. Yonezawa, S. Matsuoka, S. Inohara, Y. Tada, H. Sunahara, S. Ishii, Etsuya Shibayama, Y. Shinoda

引用次数: 0

An interprocessor memory access arbitrating scheme for the S-3800 vector supercomputer S-3800矢量超级计算机的处理器间存储器访问仲裁方案

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367140

T. Sakakibara, Katsuyoshi Kitai, T. Isobe, Shigeko Yazawa, Teruo Tanaka, Yoshiko Tamaki, Y. Inagami

{"title":"An interprocessor memory access arbitrating scheme for the S-3800 vector supercomputer","authors":"T. Sakakibara, Katsuyoshi Kitai, T. Isobe, Shigeko Yazawa, Teruo Tanaka, Yoshiko Tamaki, Y. Inagami","doi":"10.1109/ISPAN.1994.367140","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367140","url":null,"abstract":"Reports an instruction-based variable priority scheme which achieves high sustained memory throughput on a tightly coupled multiprocessor (TCMP) vector supercomputer. We analyze the two types of priority control for arbitrating interprocessor memory access conflict. In the case of request level priority control, mutual obstruction causes performance degradation, while in the case of fixed priority control, it is caused by memory bank occupation. Mutual obstruction is caused by requests of different instructions that interfere with each other, and memory bank occupation is caused by continuous accessing of the same memory bank by higher priority instructions. The instruction-based variable priority scheme works as follows: (1) the priority of each pipeline is usually changed at the end of an instruction. (2) The priority is changed more than once in the middle of an instruction, such as a stride multiple-of-8 or indirect access instruction which may occupy the same memory bank by itself. This strategy reduces mutual obstruction because the priority of each pipeline is stable in the middle of an instruction. It also reduces memory bank occupation because opportunity for memory access among different instructions is made equal by changing the priority at the end of on instruction. Moreover, it prevents memory bank occupation by stride multiple-of-8 or indirect access instruction, by changing the priority more frequently. Consequently, high sustained memory throughput can be achieved on TCMP vector supercomputers. We implemented this scheme in Hitachi's S-3800 supercomputer.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125735310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advanced fault tolerant routing in hypercubes 超多维数据集中的高级容错路由

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367147

Q. Gu, S. Peng

引用次数: 4

Cube-connected modules: a family of cubic networks 立方体连接模块:一组立方体网络

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367164

Gen-Huey Chen, Hui-Ling Huang

引用次数: 4

Performance of 4-dimensional PANDORA networks 4维PANDORA网络的性能

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367161

R. F. Holt, A. B. Ruighaver

{"title":"Performance of 4-dimensional PANDORA networks","authors":"R. F. Holt, A. B. Ruighaver","doi":"10.1109/ISPAN.1994.367161","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367161","url":null,"abstract":"The Melbourne University Optoelectronic Multicomputer Project is investigating dense optical interconnection networks capable of providing low latency data transfers of small data items. Such capabilities are useful in the exploitation of small grain parallelism. In many cases, reducing the grain size of tasks increases the amount of parallelism which can be found in the program. Our networks use an organization of data transfers called PANDORA (PArallel Newscasts on a Dense Optical Reconfigurable Array). The communication patterns on a PANDORA network are pre-determined, removing the overhead of sending and decoding addressing information. Instead the data is recognized by the time of arrival and the channel on which it arrives. Previous efforts have focused on 2-dimensional multiple broadcasting networks where each node may broadcast a different data item on the row and columns of the network. For large processor arrays, we have to reduce the density of the interconnection network as full interconnection on each row becomes too expensive. This paper discusses a 4-dimensional network which achieves a significant reduction in density with only a small increase in data transfer delays.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"66 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114036226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Undirected circulant graphs 无向循环图

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367157

F. P. Muga

引用次数: 12

Texture analysis for image processing on general-purpose parallel machines 通用并行机上图像处理的纹理分析

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367169

L. Böröczky, P. Cremonesi, N. Scarabottolo

引用次数: 1

Research on programming languages for massively parallel processing 面向大规模并行处理的编程语言研究

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367134

M. Amamiya, Masahiko Satoh, A. Makinouchi, Ken-ichi Hagiwara, T. Yuasa, H. Aida, K. Ueda, K. Araki, T. Ida, T. Baba

引用次数: 1

Efficient algorithms for conservative parallel simulation of interconnection networks 互连网络保守并行仿真的有效算法

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367188

Y. M. Teo, S. Tay

引用次数: 7

A massively parallel implementation of pattern classifiers on SIMD and MIMD architectures SIMD和MIMD架构上模式分类器的大规模并行实现

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI: 10.1109/ISPAN.1994.367170

K. Lam

{"title":"A massively parallel implementation of pattern classifiers on SIMD and MIMD architectures","authors":"K. Lam","doi":"10.1109/ISPAN.1994.367170","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367170","url":null,"abstract":"Parallel multi-layer classifier architectures with an increasing hierarchical order have offered much flexibility in design to deal with a wide variety of properties. The model of pipeline processing is especially appropriate for realising such architectures. This has provided hierarchical classifiers a distinct advantage in real-time applications to cope with the important demand for high operating speed, in addition to a potentially better classification performance. An example application of a cascaded form of the BWS and FWS networks, both of which are representatives of the array memory based statistical classifier is described in this paper. As with most pipelined architectures, the complex interactions between successive processing layers of the cascaded network represent a major drawback, and they impose performance bottlenecks which challenge the use of a highly parallel realisation of the classifier. This paper describes an efficient data parallel implementation of the BWS-FWS. For completeness, a brief review of the multi-layer classifiers is first presented. The new algorithm for combining the BWS and FWS networks is described and implemented on two distributed memory processor arrays, the MasPar MP-1 and a network of transputers. An analysis of the performance obtained is also presented.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132733135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0