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2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers最新文献

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Challenges in the design of CMOS transceivers for the IEEE 802.11 wireless LANs: past, present and future 面向IEEE 802.11无线局域网的CMOS收发器设计的挑战:过去、现在和未来
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611237
M. Zargari, S. Mehta, D. Su
{"title":"Challenges in the design of CMOS transceivers for the IEEE 802.11 wireless LANs: past, present and future","authors":"M. Zargari, S. Mehta, D. Su","doi":"10.1109/ICASIC.2005.1611237","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611237","url":null,"abstract":"The paper presents the challenges involved in the design of integrated IEEE 802.11 wireless LAN transceivers with focus on radio architecture and circuit implementation. In particular, examples of critical blocks in the receiver and transmitter are discussed.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127682551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.4-GHz ISM-transmitter IC with novel quadrature clock generation technique for a localization application 一种采用新颖正交时钟生成技术的2.4 ghz ism发射机集成电路
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489901
G. Popken, P. Baureis, M. Hartmann, H. Milosiu, H. Neubauer, F. Oehler, M. Peter
{"title":"A 2.4-GHz ISM-transmitter IC with novel quadrature clock generation technique for a localization application","authors":"G. Popken, P. Baureis, M. Hartmann, H. Milosiu, H. Neubauer, F. Oehler, M. Peter","doi":"10.1109/RFIC.2005.1489901","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489901","url":null,"abstract":"The design of a fully integrated 2.4-GHz ISM-band transmitter for a localization application is presented. The signal path includes DAC, anti-alias filter, IQ-modulator and power amplifier. The clock generation part comprises voltage controlled oscillator, phase-locked loop and a quadrature clock generator. A novel quadrature clock generation scheme is proposed and described in detail. It reduces phase errors significantly and avoids the VCO pulling problem. The circuit was fabricated in a 0.35 /spl mu/m SiGe BiCMOS technology.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123059771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Highly linear, varactor-less, 24GHz IQ oscillator 高度线性，无变量，24GHz IQ振荡器
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489879
M. Sanduleanu, E. Stikvoort
{"title":"Highly linear, varactor-less, 24GHz IQ oscillator","authors":"M. Sanduleanu, E. Stikvoort","doi":"10.1109/RFIC.2005.1489879","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489879","url":null,"abstract":"This paper presents a varactor-less, quadrature oscillator with high linearity. It is based on two identical sections comprising a differential Colpitts part and a coupling part. Tuning of the common-mode current and/or differentially changing the tail currents of the coupling and Colpitts parts can achieve the variation of the oscillation frequency. The oscillation frequency can be changed from 23 GHz to 24.4 GHz (10%) for a variation in bias current from 1 mA to 2.25 mA. The linearity in the whole tuning range is better than /spl plusmn/1.5%. The measured phase-noise @1 MHz is about -94 dBc/Hz. At a nominal supply voltage of 3.3 V/spl plusmn/10%, the supply pushing is better than 250 MHz/V. The IQ VCO has been realized in a BiCMOS process (QUBIC4) with 38 GHz f/sub T/ and 3 /spl mu/m thick top metal layer for inductors. The occupied area is 0.23 mm/sup 2/ and the power consumption is 22 mW. Possible applications for this oscillator are IQ downconverters, transceivers for mm-wave and FMCW radar sensors where the linearity of the VCO is an important design specification.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125000186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Next generation power amplifiers for wireless communications - squeezing more bits out of fewer joules 下一代无线通信功率放大器——从更少的焦耳中挤出更多的比特
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489830
L. Larson, P. Asbeck, D. Kimball
{"title":"Next generation power amplifiers for wireless communications - squeezing more bits out of fewer joules","authors":"L. Larson, P. Asbeck, D. Kimball","doi":"10.1109/RFIC.2005.1489830","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489830","url":null,"abstract":"This paper covers the limitations of current handset power amplifier design. The specific limitations on efficiency and linearity are addressed, and several of the most promising techniques for improvements are discussed.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"8 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126098919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Phase noise optimization of CMOS VCO through harmonic tuning 基于谐波调谐的CMOS压控振荡器相位噪声优化
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489825
Seonghan Ryu, Yujin Chung, Huijung Kim, Jinsung Choi, Bumman Kim
{"title":"Phase noise optimization of CMOS VCO through harmonic tuning","authors":"Seonghan Ryu, Yujin Chung, Huijung Kim, Jinsung Choi, Bumman Kim","doi":"10.1109/RFIC.2005.1489825","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489825","url":null,"abstract":"An optimization technique for a low phase noise CMOS LC VCO is proposed. The combination of harmonic tuning and on-chip filtering improves both 1/f/sup 3/ and 1/f/sup 2/ phase noise more than 10 dB over a comparable reference VCO. A 2.7 V, 5.4 mA, 30% tuning range, 1 GHz voltage controlled oscillator (VCO) is designed with the technique and implemented in a 0.35 /spl mu/m CMOS process. The optimized 1 GHz CMOS differential VCO achieves -89 dBc/Hz, -116 dBc/Hz and -135 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset frequencies from the carrier, respectively.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126102406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Properties of RFLDMOS with low resistive substrate for handset power applications 手机电源用低阻基板RFLDMOS特性研究
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489497
Juhyun Ko, Sunhak Lee, Han-Soo Oh, Joo-hyun Jeong, Donghyun Baek, Kyoungmin Koh, Jeonghu Han, Changkun Park, Songcheol Hong, Ilhun Shon
{"title":"Properties of RFLDMOS with low resistive substrate for handset power applications","authors":"Juhyun Ko, Sunhak Lee, Han-Soo Oh, Joo-hyun Jeong, Donghyun Baek, Kyoungmin Koh, Jeonghu Han, Changkun Park, Songcheol Hong, Ilhun Shon","doi":"10.1109/RFIC.2005.1489497","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489497","url":null,"abstract":"High performance lateral diffused MOSFETs on a CMOS platform have been developed for handset power applications. The LDMOS, with 0.3 /spl mu/m physical gate length and 7 nm gate oxide, shows high f/sub T/ and f/sub Max/ values up to 32 and 26 GHz, respectively, as well as low on-resistance of 3.1 ohm-mm and high saturated current of about 450 /spl mu/A//spl mu/m. The breakdown voltage is measured to be 14 V. More than 70% efficiency at 900 MHz is demonstrated in a unit power cell with a gate width of 1.92 mm.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125536212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Experimental results at one GHz on linearizing an nMOS transistor with a parallel pMOS transistor 在1 GHz频率下用并联pMOS晶体管线性化nMOS晶体管的实验结果
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489641
T. Weldon, D. Lieu, M.J. Davis
{"title":"Experimental results at one GHz on linearizing an nMOS transistor with a parallel pMOS transistor","authors":"T. Weldon, D. Lieu, M.J. Davis","doi":"10.1109/RFIC.2005.1489641","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489641","url":null,"abstract":"A simple circuit consisting of an nMOS transistor in parallel with a pMOS transistor is shown to reduce nonlinear distortion. Measured experimental results show more than 10 dB reduction in third order distortion at 1 GHz for a prototype 0.18 micron CMOS integrated circuit. Experimental data further suggest that the relative increase in the third order output intercept point greatly exceeds the corresponding increase in power supply current. Since the proposed circuit is itself a three-terminal device, it can also be used as a building block for larger circuits. Finally, theoretical linearization conditions are presented in terms of the gains and intercept points of the nMOS and pMOS devices.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114956492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 3.1-10.6 GHz ultra-wideband pulse-shaping mixer 3.1-10.6 GHz超宽带脉冲整形混频器
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489593
D. Wentzloff, A. Chandrakasan
{"title":"A 3.1-10.6 GHz ultra-wideband pulse-shaping mixer","authors":"D. Wentzloff, A. Chandrakasan","doi":"10.1109/RFIC.2005.1489593","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489593","url":null,"abstract":"This paper presents a mixer for pulse-based ultra-wideband (UWB) communication. Pulses are shaped using a new technique that accurately approximates a Gaussian pulse by exploiting the properties of a BJT. The mixer is fabricated in a 0.18 /spl mu/m SiGe BiCMOS process. Simulation and experimental results are presented.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122909069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A low-phase-noise wide-band CMOS quadrature VCO for multi-standard RF front-ends 用于多标准射频前端的低相位噪声宽带CMOS正交压控振荡器
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489868
A. Fard, Tpietro Andreani
{"title":"A low-phase-noise wide-band CMOS quadrature VCO for multi-standard RF front-ends","authors":"A. Fard, Tpietro Andreani","doi":"10.1109/RFIC.2005.1489868","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489868","url":null,"abstract":"A low phase noise CMOS LC quadrature VCO (QVCO) with a wide frequency range of 3.6-5.6 GHz, designed in a standard 0.18 /spl mu/m process for multi-standard front-ends, is presented. A significant advantage of the topology is the larger oscillation amplitude when compared to other conventional QVCO structures. The QVCO is compared to a double cross-coupled LC-tank differential oscillator, both in theory and experiments, for evaluation of its phase noise, providing a good insight into its performance. The measured data displays up to 2 dBc/Hz lower phase noise in the 1/f/sup 2/ region for the QVCO, when consuming twice the current of the differential VCO, based on an identical LC-tank. Experimental results on the QVCO show a phase noise level of -127.5 dBc/Hz at 3 MHz offset from a 5.6 GHz carrier while dissipating 8 mA of current, resulting in a figure of merit of 181.3 dBc/Hz.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129844987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A low-IF CMOS double quadrature mixer exhibiting 58 dB of image rejection for silicon TV tuners 用于硅电视调谐器的低中频CMOS双正交混频器具有58 dB的图像抑制
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers Pub Date : 2005-06-12 DOI: 10.1109/RFIC.2005.1489621
M. Notten, J. van Sinderen, F. Seneschal, F. Mounaim
{"title":"A low-IF CMOS double quadrature mixer exhibiting 58 dB of image rejection for silicon TV tuners","authors":"M. Notten, J. van Sinderen, F. Seneschal, F. Mounaim","doi":"10.1109/RFIC.2005.1489621","DOIUrl":"https://doi.org/10.1109/RFIC.2005.1489621","url":null,"abstract":"To ease full integration of a TV-receiver, a low-IF architecture has been developed. To cancel the adjacent channel at the image of the mixer, a quadrature mixer can be used with a limited image rejection of about 40 dB, which is 10 dB below the target of more than 50 dB. Therefore, a low-IF passive CMOS double quadrature mixer has been implemented which achieves high dynamic range and more than 58 dB of image rejection over a wide frequency range. The image rejection is now limited by the mismatch in the mixers and the IF polyphase filter.","PeriodicalId":135009,"journal":{"name":"2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128411469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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