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The Micro8 microcode assembler Micro8微码汇编器
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802438
Kenneth F. Greenberg
{"title":"The Micro8 microcode assembler","authors":"Kenneth F. Greenberg","doi":"10.1145/1014192.802438","DOIUrl":"https://doi.org/10.1145/1014192.802438","url":null,"abstract":"This paper describes Micro8, a commercially-available microcode assembler written in ISO standard Pascal to enhance portability. Micro8 is designed to be a useful tool for both bit-slice and discrete logic designs. Considerable flexibility in definition of the microinstruction is provided to support both vertical and horizontal microwords. Debugging assistance is included in the form of a symbol cross reference listing, a map of control store locations, and diagnostic messages. Various features provided by the assembler are described, as are examples of typical microprogram sections.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115045665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing 用于高性能科学计算的一些调度技术和易于调度的水平体系结构
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802449
B. R. Rau, C. D. Glaeser
{"title":"Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing","authors":"B. R. Rau, C. D. Glaeser","doi":"10.1145/1014192.802449","DOIUrl":"https://doi.org/10.1145/1014192.802449","url":null,"abstract":"Horizontal architectures are attractive for cost-effective, high performance scientific computing. They are, however, very difficult to schedule. Consequently, it is difficult to develop compilers that can generate efficient code for such architectures. The polycyclic architecture has been developed specifically to make the task of scheduling easy. As a result, it has been possible to develop a powerful scheduling algorithm that yields optimal and near-optimal schedules for iterative computations. This novel architecture and this scheduling algorithm are the topic of this paper.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"407 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122778054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 479
Using an oracle to measure potential parallelism in single instruction stream programs 使用oracle来测量单指令流程序中潜在的并行性
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802448
A. Nicolau, J. A. Fisher
{"title":"Using an oracle to measure potential parallelism in single instruction stream programs","authors":"A. Nicolau, J. A. Fisher","doi":"10.1145/1014192.802448","DOIUrl":"https://doi.org/10.1145/1014192.802448","url":null,"abstract":"Horizontally microprogrammable CPUs belong to a class of machines having statically schedulable parallel instruction execution (SPIE machines). Several experiments have shown that within basic blocks, real code only gives a potential speed-up factor of 2 or 3 when compacted for SPIE machines, even in the presence of unlimited hardware. In this paper, similar experiments are described. However, these measure the potential parallelism available using any global compaction method, that is, one which compacts code beyond block boundaries. Global compaction is a subject of current investigation; no measurements yet exist on implemented systems.\u0000 The approach taken is to first assume that an oracle is available during compaction. This oracle can resolve all dynamic considerations in advance, giving us the ability to find the maximum parallelism available without reformulation of the algorithm. The parallelism found is constrained only by legitimate data dependencies, since questions of conditional jump directions and unresolved indirect memory references are answered by the oracle. Using such an oracle, we find that typical scientific programs may be sped up by anywhere from 3 to 1000 times. These dramatic results provide an upper bound for global compaction techniques. We describe experiments in progress which attempt to limit the oracle progressively, with the aim of eventually producing one which provides only information that may be obtained by a very good compiler. This will give us a more practical measure of the parallelism potentially obtainable via global compaction methods.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128060709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Adaptation and personalization of VLSI-based computer architecture 基于vlsi的计算机体系结构的适应和个性化
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802435
Chiaki Ishikawa, K. Sakamura, M. Maekawa
{"title":"Adaptation and personalization of VLSI-based computer architecture","authors":"Chiaki Ishikawa, K. Sakamura, M. Maekawa","doi":"10.1145/1014192.802435","DOIUrl":"https://doi.org/10.1145/1014192.802435","url":null,"abstract":"This paper discusses the important problem of the adaptation and the personalization of VLSI-based computer systems by means of microprogramming. In order to fully exploit the VLSI chip with one million transistors on it, we propose the scheme of mass-producing the general purpose devices and then specializing them to particular application needs at the instruction set processor level and at upper levels of the computer systems. Many algorithms and examples are given. We show what facilities future computer systems should possess in the course of discussion.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"12 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128818630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A retargetable microcode generation system for a high-level microprogramming language 一种用于高级微程序设计语言的可重目标微码生成系统
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802443
P. Marwedel
{"title":"A retargetable microcode generation system for a high-level microprogramming language","authors":"P. Marwedel","doi":"10.1145/1014192.802443","DOIUrl":"https://doi.org/10.1145/1014192.802443","url":null,"abstract":"A system for the generation of microcode from a high-level microprogramming language is presented. The system is independent of the target machine because it is table-driven by a separate hardware declaration. It is applicable for horizontally microprogrammed machines.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126630323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Considerations for local compaction of nanocode for the nanodata QM-1 对纳米数据QM-1的纳米代码局部压缩的考虑
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802450
D. J. Rideout
{"title":"Considerations for local compaction of nanocode for the nanodata QM-1","authors":"D. J. Rideout","doi":"10.1145/1014192.802450","DOIUrl":"https://doi.org/10.1145/1014192.802450","url":null,"abstract":"Much work has been done recently on the problem of compaction of microcode, that of detecting parallelism between microoperations expressed in a sequential manner in order to pack the operations into as few microinstructions as possible. In particular, the theory of local compaction has developed to the stage where some extensive testing of the models and methods is called for.\u0000 This paper examines some of the considerations for local compaction of the nanocode of the Nanodata QM-1 in the context of the theoretical model of compaction presented in the literature.\u0000 This application of compaction to QM-1 nanocode not only provides a stringent test of the model, but also shows that compaction of code for this architecture is feasible, thus forming part of a test of the practicalities of developing a high-level microprogramming language for the QM-1.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116319649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Issues of the design of a low level microprogramming language for global microcode compaction 面向全局微码压缩的低级微程序设计语言的设计问题
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802440
Michael D. Poe, Ross W. Goodell, S. Steely
{"title":"Issues of the design of a low level microprogramming language for global microcode compaction","authors":"Michael D. Poe, Ross W. Goodell, S. Steely","doi":"10.1145/1014192.802440","DOIUrl":"https://doi.org/10.1145/1014192.802440","url":null,"abstract":"Microcode compaction, or packing, is the process of assigning microoperations to microwords so that the minimum number of microwords and execution time is used by the microprogram. The techniques for global microcode compaction have been described elsewhere (see below). This paper describes a proposal for an intermediate level language approach to compilation which allows machine independent global compaction. We will call the program which does this compaction the packer. This work comes from the development of the V-Compiler, a retargetable microprogram generation system1. The goal is to be able to produce very high quality microcode, while allowing code manipulations to be described and performed in an orderly manner.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117184210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automatic microcode generation for horizontally microprogrammed processors 水平微编程处理器的自动微码生成
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802447
Robert J. Sheraga, J. L. Gieser
{"title":"Automatic microcode generation for horizontally microprogrammed processors","authors":"Robert J. Sheraga, J. L. Gieser","doi":"10.1145/1014192.802447","DOIUrl":"https://doi.org/10.1145/1014192.802447","url":null,"abstract":"A procedure is described which permits applications problems coded in a Higher Level Language to be compiled to microcode for horizontally microprogrammed processors. An experimental language has been designed which is suitable for expressing computationally oriented problems for such processors in a distributed processing environment. Source programs are compiled first to a machine independent intermediate language and then to a machine dependent form consisting of elementary microoperations, with optimizations performed during each step. The microoperations are then compacted into executable microinstructions for a specific target machine. The procedure has been implemented for experimental purposes and used to compile several different types of applications programs. The experimental results are presented with an interpretation and analysis, along with recommendations for future study.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"1124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116061608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Contrasting translation, verification and synthesis in software and firmware engineering 软件和固件工程中翻译、验证和综合的对比
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802432
R. A. Mueller, G. Johnson
{"title":"Contrasting translation, verification and synthesis in software and firmware engineering","authors":"R. A. Mueller, G. Johnson","doi":"10.1145/1014192.802432","DOIUrl":"https://doi.org/10.1145/1014192.802432","url":null,"abstract":"Translation, verification and synthesis are commonly used terms in the software field, yet these terms seem to be misunderstood by many which may inhibit progress. This paper attempts, through the use of definitions and examples, to clarify these concepts and their significance in both software and firmware engineering.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121449978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
General microprogram width reduction using generator sets 一般微程序宽度减少使用发电机组
MICRO 14 Pub Date : 1981-12-01 DOI: 10.1145/1014192.802446
J. Martínez-Carballido, V. Powers
{"title":"General microprogram width reduction using generator sets","authors":"J. Martínez-Carballido, V. Powers","doi":"10.1145/1014192.802446","DOIUrl":"https://doi.org/10.1145/1014192.802446","url":null,"abstract":"The problem of reducing the microinstruction length for a parallel microprogram, by trading off microprogram width (bits) for subsequent logic, is considered. In a generalization of previous methods, it is shown that a considerable reduction of microprogram storage size can be achieved by selecting a subset of the original microorders to serve as inputs to some generating logic in order to provide all the microorders in the original microprogram. Heuristic solution methods are shown, along with ways to control the bounds of the solutions, allowing the designer the choice between a fast solution and an optimal solution. Examples show the effects of using these methods, alone and in conjunction with previously published methods for width reduction. Applications of the width reduction technique to reasonable modern design situations are discussed.","PeriodicalId":130913,"journal":{"name":"MICRO 14","volume":"24 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131002737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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