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22FDX® fMAX Optimization through Parasitics Reduction and GM Boost 22FDX®fMAX优化通过寄生降低和GM Boost
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901693
Zhixing Zhao, Pat Artz, K. Hempel, J. Faul, Tianbing Chen, Richard Taylor, J. Mazurier, C. Grass, J. Hoentschel, D. Harame, S. Lehmann, L. Lucci, Y. Andee, A. Divay, L. Pirro, T. Herrmann, A. Zaka, Ricardo Sousa
{"title":"22FDX® fMAX Optimization through Parasitics Reduction and GM Boost","authors":"Zhixing Zhao, Pat Artz, K. Hempel, J. Faul, Tianbing Chen, Richard Taylor, J. Mazurier, C. Grass, J. Hoentschel, D. Harame, S. Lehmann, L. Lucci, Y. Andee, A. Divay, L. Pirro, T. Herrmann, A. Zaka, Ricardo Sousa","doi":"10.1109/ESSDERC.2019.8901693","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901693","url":null,"abstract":"This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX®. The fMAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126130671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Temperature and Gate Leakage Influence on the Z2-FET Memory Operation 温度和栅漏对Z2-FET存储工作的影响
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901803
C. Márquez, S. Navarro, C. Navarro, Norberto Salazar, P. Galy, S. Cristoloveanu, F. Gámiz
{"title":"Temperature and Gate Leakage Influence on the Z2-FET Memory Operation","authors":"C. Márquez, S. Navarro, C. Navarro, Norberto Salazar, P. Galy, S. Cristoloveanu, F. Gámiz","doi":"10.1109/ESSDERC.2019.8901803","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901803","url":null,"abstract":"Advanced 28 nm node FD-SOI Z2-FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Experimental and 2D-TCAD results demonstrate that the memory window shifts while the retention time is reduced as the front-gate geometry is down-scaled or temperature is increased. The degradation of the memory performance can be attributed to gate tunneling current and Generation-Recombination mechanisms. The low-frequency noise and the front-gate leakage current have been experimentally studied, corroborating trap-assisted tunneling as the main degrading contributor under memory operation.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125532527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Suspended Antenna-Coupled Nanothermocouple Array for Long-Wave Infrared Detection 用于长波红外探测的悬挂式天线耦合纳米热电偶阵列
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901746
G. Szakmany, G. Bernstein, A. Orlov, W. Porod
{"title":"Suspended Antenna-Coupled Nanothermocouple Array for Long-Wave Infrared Detection","authors":"G. Szakmany, G. Bernstein, A. Orlov, W. Porod","doi":"10.1109/ESSDERC.2019.8901746","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901746","url":null,"abstract":"We study the thermal response of arrays of suspended antenna-coupled nanothermocouple (ACNTC) in response to long-wave infrared radiation. ACNTCs in the array are suspended over air-filled cavities formed in the Si substrate by XeF2 vapor etching. The cavities thermally insulate the devices from the substrate. In addition, well-designed cavities reflect the incident IR radiation and create constructive interference, thus increasing the thermal response by about 100 fold compared to previously reported devices on a substrate. Polarization-dependent measurements are presented for antenna arrays consisting of 200 devices, and we show antenna-array-size-dependent response when various numbers of ACNTCs are connected in series.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121464838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Excursion prevention and increasing device performance using mask correction for intrafield CD and Overlay improvement 偏移预防和提高设备性能使用掩模校正的内场CD和覆盖改进
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901766
Thomas Scherübl, Yael Sufrin, Avi Cohen, Ofir Sharoni, R. Seltmann
{"title":"Excursion prevention and increasing device performance using mask correction for intrafield CD and Overlay improvement","authors":"Thomas Scherübl, Yael Sufrin, Avi Cohen, Ofir Sharoni, R. Seltmann","doi":"10.1109/ESSDERC.2019.8901766","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901766","url":null,"abstract":"Advanced process control in lithography and overall patterning is of tremendous importance for advanced semiconductor Fabs to ensure chip performance and yield. The final patterning result and thus yield depend on many process parameters such as lithography processes, exposure tool performance, etch process, CMP etc. To control these effects various knobs, e.g. on the scanner for both wafer inter- and intra-field process control have been introduced, including sophisticated in-line metrology.In this paper, we will describe how device performance can be increased by improving intra-field CDU and Overlay by Mask Tuning . Mask Tuning by the ForTune system from ZEISS uses fs laser technology to locally change the mask transmission which results in improved intra field CDU on wafer (CDC™) [1],[2],[3]. As a result the lithographic process window is increased which leads to less defects on the wafer.By applying another fs laser technique, so-called RegC [4],[5],[6], intrafield overlay can be improved respectively.Below both techniques will be briefly described. Results for the achieved improvement of the intra-field CD uniformity and overlay will be introduced. Furthermore the impact on defect density will be shown.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134177101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Switching Speedup of the Magnetic Free Layer of Advanced SOT-MRAM 先进SOT-MRAM无磁层的开关加速
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901780
R. Orio, A. Makarov, S. Selberherr, W. Gös, J. Ender, S. Fiorentini, V. Sverdlov
{"title":"Switching Speedup of the Magnetic Free Layer of Advanced SOT-MRAM","authors":"R. Orio, A. Makarov, S. Selberherr, W. Gös, J. Ender, S. Fiorentini, V. Sverdlov","doi":"10.1109/ESSDERC.2019.8901780","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901780","url":null,"abstract":"We investigate the switching of a symmetric square and an elongated rectangular perpendicular free layer by spin-orbit torque with a magnetic field-free two-pulse scheme. The switching of the layer is achieved by utilizing the in-plane shape anisotropic magnetic field. For making the switching of a symmetric square layer deterministic, an in-plane stray field created in a part of the layer is used. The combination of the shape and stray fields accelerates the switching of the free layer significantly. A switching speedup factor of 3 to 5 has been obtained. The strategy also improves the robustness of the scheme allowing fast, sub-0.5 ns switching, less sensitive to the pulses’ properties.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115985870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Program Accuracy and Random Telegraph Noise on the Performance of a NOR Flash-based Neuromorphic Classifier 程序精度和随机电报噪声对基于NOR flash的神经形态分类器性能的影响
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901751
G. Malavena, Simone Petrò, A. Spinelli, C. M. Compagnoni
{"title":"Impact of Program Accuracy and Random Telegraph Noise on the Performance of a NOR Flash-based Neuromorphic Classifier","authors":"G. Malavena, Simone Petrò, A. Spinelli, C. M. Compagnoni","doi":"10.1109/ESSDERC.2019.8901751","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901751","url":null,"abstract":"In this work, we investigate the impact of program accuracy and of the time instabilities in cell threshold-voltage (VT) arising from random telegraph noise (RTN) on the performance of a neuromorphic digit classifier exploiting NOR Flash arrays as artificial synaptic arrays. First, by modeling cell VT placement resulting from a program-and-verify algorithm based on incremental step pulse programming (ISPP) in the presence of program noise, the classifier truthfulness is investigated as a function of the discretization step of the verify level and of the cell control-gate–to–floating-gate capacitance. Then, the degradation of the classifier accuracy due to RTN fluctuations displacing cell VT from its programmed value is addressed as a function of the most relevant RTN statistical parameter, i.e., the average value of the single-trap fluctuation amplitude. Results highlight some quantitative criteria to determine how scaled NOR Flash cells and arrays can be when targeting neuromorphic applications.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122088047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Investigations on current filamentation in PIN diodes using TLP measurements and TCAD simulations 利用TLP测量和TCAD模拟研究PIN二极管中的电流灯丝
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901689
P. Scharf, C. Sohrmann, S. Holland, V. Beyer
{"title":"Investigations on current filamentation in PIN diodes using TLP measurements and TCAD simulations","authors":"P. Scharf, C. Sohrmann, S. Holland, V. Beyer","doi":"10.1109/ESSDERC.2019.8901689","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901689","url":null,"abstract":"Electrostatic discharge (ESD) can be considered as one of the main reliability risks for modern electronic systems which causes failure of semiconductor devices by an over current effect. One of the dominant failure mechanisms during an ESD event is thermal runaway caused by an avalanche breakdown characterized by a negative differential resistance. A current filament is very localized and inhomogeneous and causes damage due to self-heating, gate oxide or junction breakdown. In addition this coupled electro-thermal problem can exhibit a dynamic pattern which is also known as current filament motion. Here, the formation and motion of current filaments is investigated on p+/n−/n+ (PIN) diodes using technology computer-aided design (TCAD) simulations and transmission line pulse (TLP) measurements. Special PIN diodes of different shape and size were fabricated and investigated in detail. Multiple filament formation has been observed in TLP measurements and is discussed by means of TCAD simulations.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128788554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-Noise and High-Efficiency Near-IR SPADs in 110nm CIS Technology 110nm CIS技术中的低噪声、高效率近红外spad
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901757
I. Vornicu, F. Bandi, R. Carmona-Galán, Ángel Rodríguez-Vázquez
{"title":"Low-Noise and High-Efficiency Near-IR SPADs in 110nm CIS Technology","authors":"I. Vornicu, F. Bandi, R. Carmona-Galán, Ángel Rodríguez-Vázquez","doi":"10.1109/ESSDERC.2019.8901757","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901757","url":null,"abstract":"Photon detection at longer wavelengths is much desired for LiDAR applications. Silicon photodiodes with deeper junctions and larger multiplication regions are in principle more sensitive to near-IR photons. This paper presents the complete electro-optical characterization of a P-well/ Deep N-well singlephoton avalanche diodes integrated in 110nm CMOS image sensor technology. The performance of time-of-flight image sensors is determined by the characteristics of the individual SPADs. In order to fully characterize this technology, devices with various sizes, shapes and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is of 18V. The proposed structure has 0.4Hz/µm2 dark count rate, 0.5% afterpulsing, 188ps FWHM (total) jitter and around 10% photon detection probability at 850nm wavelength. All figures have been measured at 3V excess voltage.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123302004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Test Chip for Identifying Spice-Parameters of Cryogenic BiFET Circuits 低温biet电路香料参数识别测试芯片
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901773
O. Dvornikov, N. Prokopenko, V. Tchekhovski, Y. Galkin, Alexei V. Kunz, A. Bugakova
{"title":"Test Chip for Identifying Spice-Parameters of Cryogenic BiFET Circuits","authors":"O. Dvornikov, N. Prokopenko, V. Tchekhovski, Y. Galkin, Alexei V. Kunz, A. Bugakova","doi":"10.1109/ESSDERC.2019.8901773","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901773","url":null,"abstract":"The article considers a bipolar field-effect (BiFET) test chip, designed to measure volt-ampere characteristics (VAC) of active and passive integrated elements, as well as the frequency of ring oscillators (RO) at cryogenic temperatures. The feature of the RO is the implementation of frequency-assigning capacitors on p-n-junctions of the transistors under study. A method for identifying the temperature coefficients of Spice-parameters based on VAC measurements of the RO elements and frequency is described.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":" 35","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114087879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Generation of oxide traps in Back-Side-Illuminated CMOS Image Sensors and impact on reliability 背照式CMOS图像传感器中氧化阱的产生及其对可靠性的影响
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) Pub Date : 2019-09-01 DOI: 10.1109/ESSDERC.2019.8901726
A. Vici, F. Russo, N. Lovisi, A. Marchioni, A. Casella, F. Irrera
{"title":"Generation of oxide traps in Back-Side-Illuminated CMOS Image Sensors and impact on reliability","authors":"A. Vici, F. Russo, N. Lovisi, A. Marchioni, A. Casella, F. Irrera","doi":"10.1109/ESSDERC.2019.8901726","DOIUrl":"https://doi.org/10.1109/ESSDERC.2019.8901726","url":null,"abstract":"A systematic characterization of peripheral transistors in Front-Side and Back-Side-Illuminated CMOS Image Sensors is presented. Experimental results are supported by electrostatic simulations of the gate stack. The out-coming picture is that a distribution of border traps is generated in the gate oxide in the Back-Side configuration during the wafer flipping/bonding/thinning and via opening loop. It shifts the flatband voltage, increases the channel leakage current and alters the oxide electric field. Different reliability tests demonstrate that in the Back-Side-Illuminated configuration lifetime is degraded respect to the Front-Side one, due to the particular features of that trap distribution.","PeriodicalId":128717,"journal":{"name":"ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115865331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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