2018 IEEE International Workshop on Signal Processing Systems (SiPS)最新文献

Arithmetic Computations Based on Chemical Reaction Networks 基于化学反应网络的算术计算

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/SiPS.2018.8598296

Yuchen Zhuang, Chongzhou Fang, Zaichen Zhang, X. You, Chuan Zhang

引用次数: 1

LoTTA: Energy-Efficient Processor for Always-On Applications LoTTA:用于始终在线应用的高能效处理器

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/SiPS.2018.8598408

Joonas Multanen, Heikki O. Kultala, P. Jääskeläinen, T. Viitanen, Aleksi Tervo, J. Takala

{"title":"LoTTA: Energy-Efficient Processor for Always-On Applications","authors":"Joonas Multanen, Heikki O. Kultala, P. Jääskeläinen, T. Viitanen, Aleksi Tervo, J. Takala","doi":"10.1109/SiPS.2018.8598408","DOIUrl":"https://doi.org/10.1109/SiPS.2018.8598408","url":null,"abstract":"Various use cases in the era of Internet-of-Things (IoT) demand processor devices to have low energy consumption in order to maximize the battery life. In addition to energy constraints, there is often a need to both swiftly execute control-oriented code to provide low reaction times and to occasionally perform real time signal processing tasks efficiently. As a response to these requirements, we propose LoTTA, an extremely energy-efficient exposed datapath core. Its transport-triggered programming model helps in lowering the execution latency via low cost data forwarding. Control efficiency is achieved by an optimized control unit with zero delay slot branches and predicated execution. An instruction register file is included for frequently executed program hot spots to reduce the instruction stream energy consumption. These features allow the processor to execute CHStone and EEMBC CoreMark benchmarks on average with 19% fewer cycles compared to a 6-stage LM32, a traditional RISC core with similar datapath resources. The core consumes 53% less energy on average compared to the RISC core. When including the instruction stream overheads, in the best case, LoTTA saves 79% energy, and on average 40%.","PeriodicalId":124158,"journal":{"name":"2018 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115088292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Enhanced Intra Prediction Mode Coding by using Reference Samples 基于参考样本的增强内预测模式编码

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/SiPS.2018.8598421

Promila Agarwal, Minqiang Jiang, N. Ling, Jianhua Zheng, Philipp Zhang

引用次数: 1

[Title page] (标题页)

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/sips.2018.8598343

引用次数: 0

RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing RECache:用于高效神经计算的rom嵌入式8晶体管SRAM缓存

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/SiPS.2018.8598290

Amogh Agrawal, K. Roy

{"title":"RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing","authors":"Amogh Agrawal, K. Roy","doi":"10.1109/SiPS.2018.8598290","DOIUrl":"https://doi.org/10.1109/SiPS.2018.8598290","url":null,"abstract":"One of the fast ways of evaluating complex math tables, transcendental functions, high-order polynomials etc. is by storing them in read-only memories (ROMs). However, storing large dedicated ROMs on-chip is not feasible as they incur large area overhead. Moreover, that part of the chip lies waste when ROMs are not in use. To that effect, we show at least three proposals to embed ROMs into on-chip caches using standard 8-transistor static random access memories (SRAMs). Just by adding an extra word-line (WL) or a source-line (SL), the same bit-cell can store a RAM bit, as well as a ROM bit, while maintaining the performance and area-efficiency of standard SRAMs. Moreover, due to the decoupled read/write port of the 8T-SRAMs, RAM data is not destroyed during ROM accesses, unlike prior works. We demonstrate the effectiveness of using such ROM-Embedded RAMs as caches (RECache). An improvement of up-to 19.4× in cache performance was achieved by using RECache under ‘ROM-intensive’ workloads. Further, we expand the scope of RECache, and demonstrate its applicability in specialized neural hardware. Taking an example of spiking neural network (SNN) acceleration, an energy improvement of 1.7× and iso-area performance improvement of 1.9 × was achieved with RECache, compared to standard SRAM caches.","PeriodicalId":124158,"journal":{"name":"2018 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122601266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Energy Modeling of Cluster System 集群系统的能量建模

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/SiPS.2018.8598317

Xunfei Jiang, Yuhong Liu, X. Ruan, Tuguldur Baigalmaa, Lam Nguyen, Daiki Akiyoshi, Charles Peck

引用次数: 0

[Copyright notice] (版权)

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/sips.2018.8598391

引用次数: 0

Expectation Propagation Detection with Neumann-Series Approximation for Massive MIMO 大规模MIMO的Neumann-Series逼近期望传播检测

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/SiPS.2018.8598353

Yaping Zhang, Zhizhen Wu, Chunguo Li, Zaichen Zhang, X. You, Chuan Zhang

{"title":"Expectation Propagation Detection with Neumann-Series Approximation for Massive MIMO","authors":"Yaping Zhang, Zhizhen Wu, Chunguo Li, Zaichen Zhang, X. You, Chuan Zhang","doi":"10.1109/SiPS.2018.8598353","DOIUrl":"https://doi.org/10.1109/SiPS.2018.8598353","url":null,"abstract":"For massive multiple-input multiple-output (MIMO) systems, signal detection is always a key concern. Traditional detection methods such as minimum mean square error (MMSE) all suffer from a variety of problems in respect of complexity and performance when applied to large-scale MIMO systems. In this paper, expectation propagation (EP) algorithm is employed to guarantee high-accuracy and low-complexity of symbol detection in high-dimensional MIMO systems. Nevertheless, in the iterative updating process of EP algorithm, the inevitable matrix inversion operation is one of the key challenges to the realistic hardware implementation. Therefore, a new improved EP, which is termed as expectation propagation with Neumann-series approximation (EP-NSA), is firstly proposed to accommodate the complexity as well as the performance by executing an approximate matrix inversion with a small number of Neumann-series terms. Simulation results have shown that the proposed EP-NSA with two items achieves notable performance improvement compared to belief propagation (BP) detection when the system loading factor is relatively large. For antenna configurations with large loading factor, this approach achieves similar performance to MMSE while keeping lower computational complexity.","PeriodicalId":124158,"journal":{"name":"2018 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132507707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

A Genetic Algorithm for Designing Uncoded Space-Time Labelling Diversity Mappers 一种设计无编码时空标记多样性映射的遗传算法

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/SiPS.2018.8598435

Sulaiman Saleem Patel, T. Quazi, Hongjun Xu

引用次数: 12

Parallel Wavelet-based Bayesian Compressive Sensing based on Gibbs Sampling 基于吉布斯采样的并行小波贝叶斯压缩感知

2018 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2018-10-01 DOI: 10.1109/SiPS.2018.8598375

Jian Zhou, C. Chakrabarti

{"title":"Parallel Wavelet-based Bayesian Compressive Sensing based on Gibbs Sampling","authors":"Jian Zhou, C. Chakrabarti","doi":"10.1109/SiPS.2018.8598375","DOIUrl":"https://doi.org/10.1109/SiPS.2018.8598375","url":null,"abstract":"Bayesian compressive sensing (BCS) helps address ill-posed signal recovery problems using the Bayesian estimation framework. Gibbs sampling is a technique used in Bayesian estimation that iteratively draws samples from conditional posterior distributions. However, Gibbs sampling is inherently sequential and existing parallel implementations focus on reducing the communication between computing units at the cost of increase in recovery error. In this work, we propose a two-stage parallel coefficient update scheme for wavelet-based Bayesian compressive sensing, where the first stage approximates the real distributions of the wavelet coefficients and the second stage computes the final estimate of the coefficients. While in the first stage the parallel computing units share information with each other, in the second stage, the parallel units work independently. We propose a new coefficient update scheme that updates coefficients in both stages based on data generated a few rounds ago. Such a scheme helps in relaxing the timing constraints for communication in the first stage and computations in the second stage. We design the corresponding parallel architecture and synthesize it in 7 nm technology node. We show that in a system with 8 computing units, our method helps reduce the execution time by 17.4× compared to a sequential implementation without any increase in the signal recovery error.","PeriodicalId":124158,"journal":{"name":"2018 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134628786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2