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2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)最新文献

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OCTO+: Optimized Checkpointing of B+ Trees for Non-Volatile Main Memory Wear-Leveling OCTO+:非易失性主存损耗均衡优化的B+树检查点
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628460
Christian Hakert, Roland Kühn, Kuan-Hsun Chen, Jian-Jia Chen, J. Teubner
{"title":"OCTO+: Optimized Checkpointing of B+ Trees for Non-Volatile Main Memory Wear-Leveling","authors":"Christian Hakert, Roland Kühn, Kuan-Hsun Chen, Jian-Jia Chen, J. Teubner","doi":"10.1109/nvmsa53655.2021.9628460","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628460","url":null,"abstract":"Steady deployment of byte addressable non-volatile memories (NVMs) as main memory in server class computers yields challenges on software. In order to overcome shortcomings, as for instance low cell endurance and high access latencies, working data can be kept in DRAM and continuously be checkpointed to the NVM. Although this reduces the impact of the NVM on usual execution, it shifts the endurance and latency issue to the checkpointing. Alongside widely studied generic wear-leveling solutions, we propose an application cooperative wear-leveling scheme for $mathrm{B}^{+}$ trees, that realizes an interplay of the application and the wear-leveling. We collect memory usage statistics during tree operations and dynamically choose a memory mapping between the DRAM footprint and the NVM checkpoint of the $mathrm{B}^{+}$ tree. In an experimental evaluation, we achieve $3 times$ improvement in terms of memory lifetime.","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133529331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Approximate Programming Design for Enhancing Energy, Endurance and Performance of Neural Network Training on NVM-based Systems 基于nvm系统的神经网络训练能量、耐力和性能的近似规划设计
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628582
Chien-Chung Ho, Wei-Chen Wang, Te-Hao Hsu, Zhi-Duan Jiang, Yung-Chun Li
{"title":"Approximate Programming Design for Enhancing Energy, Endurance and Performance of Neural Network Training on NVM-based Systems","authors":"Chien-Chung Ho, Wei-Chen Wang, Te-Hao Hsu, Zhi-Duan Jiang, Yung-Chun Li","doi":"10.1109/nvmsa53655.2021.9628582","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628582","url":null,"abstract":"Recently, it is found non-volatile memories (NVMs) offer opportunities for mitigating issues of neural network training on DRAM-based systems by taking advantage of its near-zero leakage power and high scalability properties. However, it brings the new challenges on energy consumption, lifetime and performance degradation caused by the massive weight/bias updates performed during training phases. To tackle these issues, this work proposes an approximate write-once memory (WOM) code method with considering the characteristics of weight updates and error tolerability of NNs. In particular, the proposed method aims to effectively reduce the number of writes on NVMs. The experimental results demonstrate that great enhancement on energy consumption, endurance and write performance can be simultaneously achieved without sacrificing the inference accuracy.","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131175389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PMap: A Non-volatile Lock-free Hash Map with Open Addressing PMap:具有开放寻址的非易失性无锁哈希映射
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628805
Kenneth Lamar, Christina L. Peterson, D. Dechev, R. Pearce, Keita Iwabuchi, P. Pirkelbauer
{"title":"PMap: A Non-volatile Lock-free Hash Map with Open Addressing","authors":"Kenneth Lamar, Christina L. Peterson, D. Dechev, R. Pearce, Keita Iwabuchi, P. Pirkelbauer","doi":"10.1109/nvmsa53655.2021.9628805","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628805","url":null,"abstract":"Non-volatile memory (NVM) is an emerging memory technology that provides data persistence and higher densities than conventional DRAM. The release of Intel Optane DC memory makes NVM a practical and testable technology. Hash maps are fundamental data structures that associatively map keys to values, offering constant time lookup. In this work, we designed a scalable, persistent hash map, PMap, optimized around large graph processing workloads. PMap is a lock-free non-volatile hash map with open addressing. Open addressing offers low memory overhead and improved cache locality when compared with node-based alternatives. Lock-freedom ensures scalable performance, and its nonblocking nature enables log-free persistence. Our hash map is supported by a non-blocking, parallel resize, which allows operations to be performed by other threads during a resize. In our performance tests, we found that our design outperformed state-of-the-art alternatives, averaging 3122x faster under Optane DC.","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114521519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Exploring Skyrmion Racetrack Memory for High Performance Full-Nonvolatile FTL 探索Skyrmion赛道存储器用于高性能全非易失性超光速
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628788
Ya-Hui Yang, Yu-Pei Liang, Cheng-Hsiang Tseng, Shuo-Han Chen
{"title":"Exploring Skyrmion Racetrack Memory for High Performance Full-Nonvolatile FTL","authors":"Ya-Hui Yang, Yu-Pei Liang, Cheng-Hsiang Tseng, Shuo-Han Chen","doi":"10.1109/nvmsa53655.2021.9628788","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628788","url":null,"abstract":"Skyrmion racetrack memory (SK-RM) has shown great potential for replacing DRAM or SRAM with its high density and great access performance. Unlike other non-volatile random access memory (NVRAM), SK-RM supports random updates through injecting or removing skyrmions on a racetrack. Injected skyrmions can be shifted along the racetrack to store data. Nevertheless, since most previous studies focus on minimizing the number of inject or shift operations, the unique feature of moving skyrmions vertically between racetracks and the possibility of utilizing free or invalid memory space to preserve skyrmions receive much less attention. In this paper, we observe that vertical movement and preservation of skyrmions provide a great opportunity to mitigate the possible run time performance degradation issue of NVRAM-based flash translation layer (FTL), as writes of mapping entries typically induce more overhead than reads on NVRAM. To fully exploit the benefits of SK-RM within the FTL mechanism, this paper proposes an SK-FTL to enable a high-performance and non-volatile FTL by preserving and reforming skyrmions over multiple data writes. Experimental results suggest that SK-FTL can effectively improve the performance of non-volatile FTL.","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116743848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Designing a persistent-memory-native storage engine for SQL database systems 为SQL数据库系统设计持久内存本地存储引擎
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628842
S. Matsuura
{"title":"Designing a persistent-memory-native storage engine for SQL database systems","authors":"S. Matsuura","doi":"10.1109/nvmsa53655.2021.9628842","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628842","url":null,"abstract":"We illustrate the design of our in-house storage engine for SQL database systems. The storage engine is designed to be persistent-memory native, meaning that database and transaction log files are placed on persistent memory and accessed with byte granularity from the storage engine. In addition, it is aimed to be practical in industry and highly performant with the use of persistent memory. In this paper, we discuss five essential requirements for such a storage engine to be practical in industry and how they are met in our in-house storage engine. Furthermore, we highlight two important design features, namely, (1) the pre-fault feature and (2) the parallel-logging feature, that have been incorporated to our in-house storage engine, to improve its performance. By meeting the five essential requirements and incorporating the two design features to our in-house storage engine, we implement a persistent-memory-native storage engine for SQL database systems, in-house, that satisfies industry requirements and that is highly performant on write workload on persistent memory.","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130802592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NVMSA 2021 Cover Page NVMSA 2021封面
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628407
{"title":"NVMSA 2021 Cover Page","authors":"","doi":"10.1109/nvmsa53655.2021.9628407","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628407","url":null,"abstract":"","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133374116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier 使用两位电流模式感应放大器的非易失性内存计算ReRAM宏
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628563
Qiqiao Wu, Wenhao Sun, Junpeng Wang, Xuefei Bai, Feng Zhang, Song Chen, Yi Kang
{"title":"A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier","authors":"Qiqiao Wu, Wenhao Sun, Junpeng Wang, Xuefei Bai, Feng Zhang, Song Chen, Yi Kang","doi":"10.1109/nvmsa53655.2021.9628563","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628563","url":null,"abstract":"The non-volatile memories such as FeRAM, PcRAM, and ReRAM afford an innovative approach to the computing in memory (CIM) architecture, which is promising to solve the memory wall problem in the traditional Von Neumann architecture. This paper proposes ReRAM-based CIM architecture, which does multiplication and accumulation in the ReRAM array with low power consumption and saves the bandwidth of the storage unit and the processing unit. We combine the CIM architecture with digital circuits to verify the speaker recognition function based on the Long Short-Term Memory (LSTM) network. Moreover, We propose a Two-bit Current-Mode Sensing Amplifier (2b-CSA) as an interface between analog and digital to improve throughput and energy efficiency. This work is simulated under the CMOS 180nm process for compatibility with embedded ReRAM and CMOS logic. The result shows that this work can achieve a CIM operation energy consumption of 1.6pJ per bit.","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme 基于模式修剪的权重映射方案的高面积/能量效率RRAM CNN加速器
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628683
Songming Yu, Lu Zhang, Jingyu Wang, Jinshan Yue, Zhuqing Yuan, Xueqing Li, Huazhong Yang, Yongpan Liu
{"title":"High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme","authors":"Songming Yu, Lu Zhang, Jingyu Wang, Jinshan Yue, Zhuqing Yuan, Xueqing Li, Huazhong Yang, Yongpan Liu","doi":"10.1109/nvmsa53655.2021.9628683","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628683","url":null,"abstract":"Resistive random access memory (RRAM) is an emerging device for processing-in-memory (PIM) architecture to accelerate convolutional neural network (CNN). However, due to the highly coupled crossbar structure in the RRAM array, it is difficult to exploit the CNN sparsity feature to improve the performance in RRAM-based CNN accelerator. To optimize the weight mapping of sparse network in the RRAM array and improve area and energy efficiency, we propose a novel weight mapping scheme and corresponding RRAM-based CNN accelerator architecture based on pattern pruning and operation unit(OU) mechanism. Experimental results show that our work can achieve 4.16x-5.20x crossbar area efficiency, 1.98x2.15x energy efficiency, and 1.15x-1.35x performance speedup in comparison with the traditional method.","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122185776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
NVMSA 2021 Index NVMSA 2021指数
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628553
{"title":"NVMSA 2021 Index","authors":"","doi":"10.1109/nvmsa53655.2021.9628553","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628553","url":null,"abstract":"","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122279312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density 一种新型的多上下文非易失性内容可寻址存储单元和高可靠性、高密度的多级结构
2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2021-08-18 DOI: 10.1109/nvmsa53655.2021.9628720
Xianggao Wang, Deming Zhang, Kaili Zhang, E. Deng, You Wang, Weisheng Zhao
{"title":"A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density","authors":"Xianggao Wang, Deming Zhang, Kaili Zhang, E. Deng, You Wang, Weisheng Zhao","doi":"10.1109/nvmsa53655.2021.9628720","DOIUrl":"https://doi.org/10.1109/nvmsa53655.2021.9628720","url":null,"abstract":"Currently, non-volatile content-addressable memory (NV-CAM) based on magnetic tunnel junction (MTJ) has huge potential in search applications, owing to its non-volatility, zero standby power and high speed. However, it still suffers from severe reliability and energy dissipation issues especially when the searched data information is large. To address these issues, we propose a multi-context cell (MCC) circuit by employing an output selector (OS) instead of a logic tree (LT) and a multi-level architecture (MLA) by employing SEN generators. In this proposed M-level NV-CAM (e.g., M=2), every M IT/2MTJ memory cells share one search circuit composed of a M-level selector, a pre-charge sense amplifier (PCSA), a OS and a math-line (ML) switch to improve area efficiency, and the search circuit together with M memory cells combine into a MCC. Moreover, the search-enable signal SEN influenced by ML can bring inessential search operations inactivity. Hybrid 40nm CMOS/MTJ simulation results show that the proposed MCC circuit can reach a lower search-error-rate (SER) of 0.5 % and a lower search delay of 39.45 ps compared with the previous (a) cell circuit with LT. On the other hand, the SER of searching a 144-bit data information in the proposed 2-1evel-architecture NV-CAM can be only 4.5 %, about 2.93 times lower than that in the traditional-architecture NV-CAM.","PeriodicalId":122428,"journal":{"name":"2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128101765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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