IEEE/ACM International Symposium on Low Power Electronics and Design最新文献_第3页

Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation 具有pvt感知锁定范围补偿的近/亚阈值dll时钟发生器

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993597

Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, W. Hwang

{"title":"Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation","authors":"Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, W. Hwang","doi":"10.1109/ISLPED.2011.5993597","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993597","url":null,"abstract":"A near-/sub-threshold programmable clock generator is proposed in this paper. The major challenge of the ultra-low voltage (ULV) circuits is that the lock-in range of the delay line is easily affected by the environmental variations. In the proposed clock generator, there is a PVT compensation unit which consists of a set of delay line and a PVT detector. The unit is responsible for adjusting the lock-in range of clock generator to guarantee successful clock lock. In addition, the variation-aware logic design is performed in the clock generator, which improves the reliability on process variation. Also, the adoption of pulse-circulating scheme suppresses process induced output clock jitter. Furthermore, it has the ability to generate the output clock with frequency from 1/8 to 4 times of the reference clock. The clock generator has been designed using UMC 65nm CMOS technology. The frequencies of reference clock are 625 kHz at 0.2V and 5MHz at 0.5V. The power consumptions are 0.18μW and 5.17μW, respectively, at 0.2V and 0.5V. The core area of this clock generator is 0.01mm2.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"21 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114023877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

TLB index-based tagging for cache energy reduction 基于TLB索引的缓存能量降低标记

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.5555/2016802.2016828

Jongmin Lee, Seokin Hong, Soontae Kim

引用次数: 13

Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling 通过细粒度电流调节和电压升级提高相变存储器寿命

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993624

Lei Jiang, Youtao Zhang, Jun Yang

引用次数: 35

8T Single-ended sub-threshold SRAM with cross-point data-aware write operation 8T单端亚阈值SRAM，具有交叉点数据感知写操作

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993631

Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, S. Jou, C. Chuang

引用次数: 26

Eliminating energy of same-content-cell-columns of on-chip SRAM arrays 消除片上SRAM阵列中同内容单元列的能量

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993633

Bushra Ahsan, Lorena Ndreu, I. Sideris, Yiannakis Sazeides, Sachin Idgunji, E. Özer

引用次数: 6

A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems 一种快速、准确、简单的关键路径监测方法，用于改善分布式交换机系统的能量延迟积

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993672

Junyoung Park, J. Abraham

{"title":"A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems","authors":"Junyoung Park, J. Abraham","doi":"10.1109/ISLPED.2011.5993672","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993672","url":null,"abstract":"This paper introduces a design scheme that improves Energy-Delay Product (EDP) in conventional Dynamic Voltage Scaling (DVS) systems by exploiting timing margins. To achieve this scheme, we designed a high-speed Critical Path Monitor composed of several Critical Path Replicas, a Timing Checker, and a Toggle Flip-Flop. The replicas are implemented based on our proposed algorithm, which considers the following two facts: (a) the voltage scaling behavior of logic and interconnect are fundamentally different; (b) various logic gates show different sensitivity in regard to process, temperature, as well as voltage changes. Because the replicas are connected in parallel by C-elements, the longest delay selection among all of the replica delays is performed automatically, improving the system response time. If the utilizable margin is detected by the Timing Checker, the frequency controller increases system clock frequency in order to improve performance at a given voltage level. Using a 45nm CMOS technology, we implemented a 32-bit MIPS processor and multiple Critical Path Monitors. The simulation results reveal that our scheme can improve EDP of the conventional DVS by up to 62%.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

IMPACT: IMPrecise adders for low-power approximate computing 影响:低功耗近似计算的不精确加法器

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993675

Vaibhav Gupta, Debabrata Mohapatra, S. P. Park, A. Raghunathan, K. Roy

{"title":"IMPACT: IMPrecise adders for low-power approximate computing","authors":"Vaibhav Gupta, Debabrata Mohapatra, S. P. Park, A. Raghunathan, K. Roy","doi":"10.1109/ISLPED.2011.5993675","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993675","url":null,"abstract":"Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, the final output is interpreted by human senses, which are not perfect. This fact obviates the need to produce exactly correct numerical outputs. Previous research in this context exploits error-resiliency primarily through voltage over-scaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate Full Adder (FA) cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units, and evaluate them to demonstrate the efficacy of our approach. Post-layout simulations indicate power savings of up to 60% and area savings of up to 37% with an insignificant loss in output quality, when compared to existing implementations.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133448036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 450

Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs 电压标度位交错8-T ram的动态与静态可写性分析

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993627

Daeyeon Kim, V. Chandra, R. Aitken, D. Blaauw, D. Sylvester

{"title":"Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs","authors":"Daeyeon Kim, V. Chandra, R. Aitken, D. Blaauw, D. Sylvester","doi":"10.1109/ISLPED.2011.5993627","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993627","url":null,"abstract":"As process technology scales, SRAM robustness is compromised. In addition, lowering the supply voltage to reduce power consumption further reduces the read and write margins. To maintain robustness, a new bitcell topology, 8-T bitcell, has been proposed and read where write operation can be separately optimized. However, it can aggravate the half select disturb when write word-line boosting is applied or the bitcell sizing is done to enable robust writability. The half select disturb issue limits the use of a bit-interleaved array configuration required for immunity to soft errors. The opposing characteristic between write operation and half select disturb generates a new constraint which should be carefully considered for robust operation of voltage-scaled bit-interleaved 8-T SRAMs. In this paper, we propose bit-interleaved writability analysis that captures the double-sided constraints placed on the word-line pulse width and voltage level to ensure writability while avoiding half select disturb issue. Using the proposed analysis, we investigate the effectiveness of word-line boosting and device sizing optimization on improving bitcell robustness in low voltage region. With 57.7% of area overhead and 0.1V of word-line boosting, we can achieve 4.6σ of VTH mismatch tolerance at 0.6V and it shows 41% of energy saving.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"5 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131922980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Pulsed-latch-based clock tree migration for dynamic power reduction 基于脉冲锁存器的时钟树动态降功耗迁移

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993601

Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho

引用次数: 15

Does low-power design imply energy efficiency for data centers? 低功耗设计意味着数据中心的能源效率吗?

IEEE/ACM International Symposium on Low Power Electronics and Design Pub Date : 2011-08-01 DOI: 10.1109/ISLPED.2011.5993621

David Meisner, T. Wenisch

引用次数: 27