WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873553

A. Sinha, Zhimin Chen, P. Schaumont

{"title":"A comprehensive analysis of performance and side-channel-leakage of AES SBOX implementations in embedded software","authors":"A. Sinha, Zhimin Chen, P. Schaumont","doi":"10.1145/1873548.1873553","DOIUrl":"https://doi.org/10.1145/1873548.1873553","url":null,"abstract":"The Advanced Encryption Standard is used in almost every new embedded application that needs a symmetric-key cipher. In such embedded applications, high-performance as well as resistance against implementation attacks is mandatory. In this paper, we compare and contrast three different software implementations of AES. The first two are based on cryptographic lookup tables, while the third uses bit-slicing. We analyze the performance and side-channel resistance of each implementation on two different FPGA platforms, one based on a PowerPC processor, and the second based on a LEON-3 soft-core processor. Our measurements show that, on embedded platforms, a bit-sliced AES implementation does not always outperform a lookup-table based AES implementation. We also present a detailed analysis of the side-channel resistance and the source of side-channel leakage, and show that our bit-sliced implementation has eight times more side-channel leakage than the lookup-table implementations. Hence, we conclude that a variation on the implementation style for embedded software implementation of AES will not only affect performance, but also embedded system security.","PeriodicalId":114446,"journal":{"name":"WESS '10","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114231266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessors PoliMakE:一个策略制定引擎，用于在芯片多处理器上安全执行嵌入式软件

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873550

L. A. Bathen, N. Dutt

{"title":"PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessors","authors":"L. A. Bathen, N. Dutt","doi":"10.1145/1873548.1873550","DOIUrl":"https://doi.org/10.1145/1873548.1873550","url":null,"abstract":"Secure software execution on chip-multiprocessor platforms is compromised by threats such as software-based side channel attacks that expose information from shared memory. The increasing amount of shared (memory or computational) resources on emerging chip-multiprocessors further exacerbates security threats, highlighting the need for secure policies to manage on-chip resources. We present PoliMakE, a methodology that enables exploration and generation of customized policies to guarantee secure software execution on a chip-multiprocessor system in the presence of software-based side channel attacks. PoliMakE analyzes an application's security needs and generates a series of custom policies that dictate how to safely execute tasks and efficiently manage the computational, communication, and memory resources. Our experimental results on DRM, JPEG as well as some synthetic applications show that PoliMakE enables secure software execution with minimal performance overhead, while reducing power consumption, since the policies are customized to efficiently utilize the available on-chip resources. For the case study of running DRM in secure mode concurrently with JPEG encoding, we are able to observe 61% performance improvement when compared to standard approaches. Our policy generation engine is able to generate policies in only a matter of minutes for secure applications with hundreds of tasks. Unsecure applications were observed to resume execution up to 99% faster than with the traditional halt approach.","PeriodicalId":114446,"journal":{"name":"WESS '10","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115800775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Countering early evaluation: an approach towards robust dual-rail precharge logic 对抗早期评估:一种实现稳健双轨预充逻辑的方法

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873554

S. Bhasin, S. Guilley, Florent Flament, Nidhal Selmane, J. Danger

{"title":"Countering early evaluation: an approach towards robust dual-rail precharge logic","authors":"S. Bhasin, S. Guilley, Florent Flament, Nidhal Selmane, J. Danger","doi":"10.1145/1873548.1873554","DOIUrl":"https://doi.org/10.1145/1873548.1873554","url":null,"abstract":"Wave Dynamic Differential Logic (WDDL) is a hiding countermeasure to thrawt side channel attacks (SCA). It suffers from a vulnerability called Early Evaluation, i.e. calculating output before all inputs are valid. This causes delay biases in WDDL even when synthesized with positive gates. s a consequence, the design can be attacked, although with extra effort, through side channel. However, WDDL is an appealing logic since it has already been reported to natively resist against multiple asymmetric faults. In this article, we suggest a Dual Rail Precharge Logic (DPL), similar to WDDL, free from early evaluation by design. We demonstrate practically that the early evaluation accounts for major part of the leakage. We also provide basic guidelines for designing such a DPL. This DPL can resist against side channel attacks and fault attacks at the same time. In line with the current security evaluation methodology, we use differential power analysis and mutual information to compare the modified WDDL with the traditional WDDL. To compare robustness w.r.t security, we conduct a proof-of-concept experiment that compares the two logics with identical implementations (P&R) apart from the logic style. The sensitive side channel leakage is reduced by half in the DPL without the early evaluation flaw.","PeriodicalId":114446,"journal":{"name":"WESS '10","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116149330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38

A new CRT-RSA algorithm resistant to powerful fault attacks 一种新的CRT-RSA算法，可抵抗强大的故障攻击

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873556

N. Ebeid, Rob Lambert

引用次数: 6

Hardware-assisted security enhanced Linux in embedded systems: a proposal 嵌入式系统中硬件辅助安全性增强的Linux:一个建议

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873551

Leandro Fiorin, A. Ferrante, Konstantinos Padarnitsas, S. Carucci

{"title":"Hardware-assisted security enhanced Linux in embedded systems: a proposal","authors":"Leandro Fiorin, A. Ferrante, Konstantinos Padarnitsas, S. Carucci","doi":"10.1145/1873548.1873551","DOIUrl":"https://doi.org/10.1145/1873548.1873551","url":null,"abstract":"As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. This is especially true for embedded systems, often operating in non-secure environments, and with limited amount of computational, storage, and communication resources available. In servers and desktop systems, Security Enhanced Linux (SELinux) is currently used as a method to enhance security by enforcing a security control based on policies that confine user programs, or processes, to the minimum amount of privileges that they require for their execution. While providing a powerful mean for enhancing security in UNIX-like systems, SELinux still remains a feature that is too heavy to be fully supported by constrained devices. In this paper, we propose a hardware architecture for enhancing security and accelerating retrieval and applications of SELinux policies in embedded processors. We describe the general ideas behind our work, discussing motivations, advantages, and limits of the solution proposed, while suggesting the main steps needed to implement the described architecture on common embedded processors.","PeriodicalId":114446,"journal":{"name":"WESS '10","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132755183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Enhancing network-on-chip components to support security of processing elements 增强片上网络组件，以支持处理元素的安全性

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873560

S. Lukovic, Nikolaos Christianos

引用次数: 26

Secure protocols for serverless remote product authentication 无服务器远程产品认证的安全协议

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873559

Abdourhamane Idrissa, A. Aubert, T. Fournel, V. Fischer

{"title":"Secure protocols for serverless remote product authentication","authors":"Abdourhamane Idrissa, A. Aubert, T. Fournel, V. Fischer","doi":"10.1145/1873548.1873559","DOIUrl":"https://doi.org/10.1145/1873548.1873559","url":null,"abstract":"Industrial companies lose large sums of money because of counterfeits and they need to efficiently protect their trademarks. Most of them implement their own anti-counterfeiting policy to deal with the menace. A number of technologies, such as holograms, smart cards, biometric markers and inks, can be employed to protect and authenticate genuine products. Instead of using markers and additional identification means, one of the recent methods use a PUF-like authentication method based on image processing. However, in order to authenticate the object (e.g. a trademark product), the method needs direct access to the database system containing the object's \"fingerprint\". The paper presents a new secure method to remotely authenticate the object without communication with the database server. In this method, an autonomous and secure embedded system called authentication device authenticates the product by extracting its morphometric fingerprint and comparing it with a signed original morphometric fingerprint printed on the object. However, we show that in order to secure the protocol, the authentication hardware needs to be authenticated, too. For this reason, we propose security protocols that allow to authenticate the authentication device and remotely check its integrity. The proposed security protocols are shown to be sure using formal methods of security protocol evaluation.","PeriodicalId":114446,"journal":{"name":"WESS '10","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122619156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new correlation frequency analysis of the side channel 一种新的侧信道相关频率分析方法

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873552

Edgar Mateos, C. Gebotys

引用次数: 33

Hardware trust implications of 3-D integration 3-D集成的硬件信任含义

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873549

Ted Huffmire, T. Levin, Michael Bilzor, C. Irvine, Jonathan Valamehr, Mohit Tiwari, T. Sherwood, R. Kastner

引用次数: 16

Improving the quality of ring oscillator PUFs on FPGAs 提高fpga环形振荡器puf的质量

WESS '10 Pub Date : 2010-10-24 DOI: 10.1145/1873548.1873557

D. Merli, F. Stumpf, C. Eckert

引用次数: 107

WESS '10最新文献