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Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)最新文献

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Rapid Phototyping of a System-on-a-Chip for the BLAST Algorithm Implementation 用于BLAST算法实现的片上系统快速影印
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.31
E. Sotiriades, C. Kozanitis, Grigorios Chrysos, A. Dollas
{"title":"Rapid Phototyping of a System-on-a-Chip for the BLAST Algorithm Implementation","authors":"E. Sotiriades, C. Kozanitis, Grigorios Chrysos, A. Dollas","doi":"10.1109/RSP.2006.31","DOIUrl":"https://doi.org/10.1109/RSP.2006.31","url":null,"abstract":"In the course of rapid system prototyping of a large scale design and implementation of the BLAST algorithm for bioinformatics, we evaluated two different design methods. First, we used the \"traditional\" method of design with modeling in C and design and synthesis using VHDL. Second, we used the automated tools MATLAB/Simulink with two different design flows, i.e. the fully automated one from MATLAB to bitstream, and, the architecture and subsystem development based on the MATLAB/Simulink results. We examine the tradeoffs between designer time, design quality and speed, and resource optimization. We analyze how modern tools such as MATLAB/Simulink can improve architecture design and facilitate \"what if\" scenarios. We conclude that conventional architecture development and design flow is still required for highly optimized system building but the architecture development capabilities of modern tools need to be assimilated in the design process","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Wcomp: a Multi-Design Approach for Prototyping Applications using Heterogeneous Resources Wcomp:使用异构资源的原型应用程序的多设计方法
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.42
Daniel Cheung-Foo-Wo, J. Tigli, S. Lavirotte, M. Riveill
{"title":"Wcomp: a Multi-Design Approach for Prototyping Applications using Heterogeneous Resources","authors":"Daniel Cheung-Foo-Wo, J. Tigli, S. Lavirotte, M. Riveill","doi":"10.1109/RSP.2006.42","DOIUrl":"https://doi.org/10.1109/RSP.2006.42","url":null,"abstract":"This paper presents Wcomp which is a framework for rapid application prototyping. This framework has been developed for targeting wearable computing applications but can also be used in the field of pervasive and context-aware computing. In the first part of the paper, we investigate the possibility of taking into consideration the relations between software components and resources of the \"operating context\" in our Wcomp platform. Secondly, we investigate the opportunity of taking a multi-designer approach in order to adapt the application to multiple well-suited representations. Then we introduce in the platform a new design approach based on patterns of interactions called ISL4Wcomp","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126186660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Rapid Performance and Power Consumption Estimation Methods for Embedded System Design 嵌入式系统设计的快速性能和功耗估计方法
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.30
S. Niar, Nicolas Inglart
{"title":"Rapid Performance and Power Consumption Estimation Methods for Embedded System Design","authors":"S. Niar, Nicolas Inglart","doi":"10.1109/RSP.2006.30","DOIUrl":"https://doi.org/10.1109/RSP.2006.30","url":null,"abstract":"As embedded systems increase in complexity, rapid performance estimation methods, appropriate for use early in the design process, are becoming more and more necessary. These methods can produce significant decreases in execution time, power consumption and system cost. However, to be practicable, a design space exploration (DSE) process must be capable of evaluating several design alternatives quickly. This paper focuses on ways to accelerate performance and power consumption evaluation for embedded systems. Three methods: statistical simulation (SS), analytical modeling and detailed simulation (AMDS) and analytical modeling and statistical simulation (AMSS), offering both speed and accuracy for detailed cycle-accurate micro-architecture simulation, are presented and compared. Experimental results indicate that these methods produce interesting simulation acceleration factors. In addition, the error margin is on average less than 3.8%, reaching 8% in the worst case","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
RTOS Scheduler Implementation in Hardware and Software for Real Time Applications 实时应用中RTOS调度器的软硬件实现
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.34
Melissa Vetromille, Luciano Ost, C. Marcon, C. Reif, Fabiano Hessel
{"title":"RTOS Scheduler Implementation in Hardware and Software for Real Time Applications","authors":"Melissa Vetromille, Luciano Ost, C. Marcon, C. Reif, Fabiano Hessel","doi":"10.1109/RSP.2006.34","DOIUrl":"https://doi.org/10.1109/RSP.2006.34","url":null,"abstract":"In order to enhance performance and improve predictability of the real time systems, implementing some critical operating system functionalities, like time management and task scheduling, in software and others in hardware is an interesting approach. Scheduling decision for real-time embedded software applications is an important problem in real-time operating system (RTOS) and has a great impact on system performance. In this paper, we evaluate the pros and cons of migrating RTOS scheduler implementation from software to hardware. We investigate three different RTOS scheduler implementation approaches: (i) implemented in software running in the same processor of the application tasks, (ii) implemented in software running in a co-processor, and (iii) implemented in hardware, while application tasks are running on a processor. We demonstrate the effectiveness of each approach by simulating and analyzing a set of benchmarks representing different embedded application classes","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130298480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Principles for System Prototype and Verification Using Metamodel Based Transformations 使用基于元模型的转换的系统原型和验证原则
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.29
Luis Pedro, L. Lucio, Didier Buchs
{"title":"Principles for System Prototype and Verification Using Metamodel Based Transformations","authors":"Luis Pedro, L. Lucio, Didier Buchs","doi":"10.1109/RSP.2006.29","DOIUrl":"https://doi.org/10.1109/RSP.2006.29","url":null,"abstract":"Using domain specific modeling (DSM) allows solutions to be expressed in the idiom and at the level of abstraction of the problem domain. However, this does not imply that prototypes can be easily and rapidly generated. In reality, domain specific languages (DSLs) are difficult to design, implement and maintain, and usually there is a potential loss of efficiency when compared with hand-coded software. In this paper we explain the principles based on which we expect to solve some of these problems by means of transformation from a DSL to a formalism with a well define semantics named concurrent object oriented Petri-nets (CO-OPN). The proposed methodology uses the metamodel of the DSL as the principle for the transformation. This transformation represents the semantic mapping between the DSL and CO-OPN. The achievement is both to provide a formally defined semantics to the DSL and, since CO-OPN is integrated in a framework, to provide the functionalities that allow model verification and fast prototype generation for the DSL","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129605312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A High Performance Parallel FIR Filters Generation Tool 一个高性能并行FIR滤波器生成工具
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.2
V. S. Rosa, E. Costa, S. Bampi
{"title":"A High Performance Parallel FIR Filters Generation Tool","authors":"V. S. Rosa, E. Costa, S. Bampi","doi":"10.1109/RSP.2006.2","DOIUrl":"https://doi.org/10.1109/RSP.2006.2","url":null,"abstract":"This paper presents generation tool and performance results on a method to minimize the amount of hardware needed to implement a parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation targeted for high performance. The generation tool employ a combination of two approaches: first, the reduction of the coefficients to n-power-of-two (NPT) terms, where the maximum number of non-zero in each coefficient is taken as a constraint, followed by common subexpression elimination (CSE) among multipliers. Synthesis results for a range of different filter specifications, using Quartus II FPGA synthesis tool are presented","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128069684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An Embedded Java Virtual Machine Using Network-on-Chip Design 基于片上网络设计的嵌入式Java虚拟机
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.7
Graham Mathias, K. Kent
{"title":"An Embedded Java Virtual Machine Using Network-on-Chip Design","authors":"Graham Mathias, K. Kent","doi":"10.1109/RSP.2006.7","DOIUrl":"https://doi.org/10.1109/RSP.2006.7","url":null,"abstract":"Virtual machine technology allows for the reuse of applications and code over various heterogeneous platforms. A virtual machine simply adds another layer of abstraction between the application and the native hardware. A major drawback of an application running on a virtual machine, however, is that the performance is below that of an application targeted for a native platform. Previous work has dealt with improving the performance of a virtual machine through hardware support using field programmable gate arrays (FPGAs). With the growing capacities of FPGAs it is becoming possible to provide higher levels of hardware support. This work examines the Java virtual machine (JVM), by implementing it in hardware, using a network-on-chip (NoC) design methodology. A subset of the JVM instructions are implemented in a hardware engine, with the more complex operations performed in software, and this hardware engine is replicated numerous times within the FPGA. By having several JVM instances execute in hardware concurrently, multiple applications and/or threads can simultaneously benefit from hardware implementation","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128350946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCs 基于soc的嵌入式多媒体应用设计空间探索案例研究
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.1
Isabelle Hurbain, Corinne Ancourt, F. Irigoin, M. Barreteau, N. Museux, F. Pasquier
{"title":"A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCs","authors":"Isabelle Hurbain, Corinne Ancourt, F. Irigoin, M. Barreteau, N. Museux, F. Pasquier","doi":"10.1109/RSP.2006.1","DOIUrl":"https://doi.org/10.1109/RSP.2006.1","url":null,"abstract":"Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost effective to exploit the underlying parallelism. However, programming applications for SIMD targets requires data placement and operation scheduling which are NP-complete problems. In this paper we show how our tool (based on concurrent constraint programming) can be used to explore the design space of a kernel in H.264 standard (video compression). Different cost functions are considered (e.g. execution time, memory occupancy, chip cost...) to derive different source codes from the same functional specification. Future work includes model refinement as well as full code generation for rapid prototyping of such hardware and software intensive systems","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132055143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Platform Development for Run-Time Reconfigurable Co-Emulation 运行时可重构协同仿真平台开发
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.28
Rawat Siripokarpirom
{"title":"Platform Development for Run-Time Reconfigurable Co-Emulation","authors":"Rawat Siripokarpirom","doi":"10.1109/RSP.2006.28","DOIUrl":"https://doi.org/10.1109/RSP.2006.28","url":null,"abstract":"Over the past few years, there has been an increasing interest in using partial and run-time reconfigurable (RTR) FPGAs to develop reconfigurable systems for various applications. To support this new type of hardware, new or improved design methodologies and tools are needed that can provide sufficient support for RTR-related design and verification tasks. This paper first introduces a novel concept called run-time reconfigurable co-emulation, which extends traditional co-emulation with the RTR capability of FPGAs. It then describes and discusses how to develop hardware platforms that use the RTR co-emulation concept for transaction-level functional verification and in-circuit debugging of RTR-based FPGA designs","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127112606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling 基于服务的灵活硬件/软件接口建模组件设计方法
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06) Pub Date : 2006-06-14 DOI: 10.1109/RSP.2006.35
L. Kriaa, A. Bouchhima, W. Youssef, F. Pétrot, A. Fouilliart, A. Jerraya
{"title":"Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling","authors":"L. Kriaa, A. Bouchhima, W. Youssef, F. Pétrot, A. Fouilliart, A. Jerraya","doi":"10.1109/RSP.2006.35","DOIUrl":"https://doi.org/10.1109/RSP.2006.35","url":null,"abstract":"This paper describes a service-based model enabling systematic design and global simulation environments for SoC design. This model, called service dependency graph (SDG) allows modeling of complex, customized (application-specific) interfaces. We also present a model generator that can automatically build hardware/software interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of a software defined radio application. The results show the effectiveness of the proposed approach in modeling complex interfaces. Additionally the SDG seems to be an excellent intermediate representation for the design automation of hardware software interfaces","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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