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2019 China Semiconductor Technology International Conference (CSTIC)最新文献

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A High Efficiency N Channel Single Poly OTP Cell Structure in Standard CMOS Process 标准CMOS制程中高效率N通道单多晶硅元结构
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755632
Yu Chen, Yuan Yuan, Hualun Chen, Yuhua Zhang
{"title":"A High Efficiency N Channel Single Poly OTP Cell Structure in Standard CMOS Process","authors":"Yu Chen, Yuan Yuan, Hualun Chen, Yuhua Zhang","doi":"10.1109/CSTIC.2019.8755632","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755632","url":null,"abstract":"A high efficiency N channel single poly OTP (One time programmable memory) cell structure is proposed in this paper. The cell consists of one NMOS transistor and one MOS capacitor. NLDD implant is blocked in the NMOS area of the cell to improve program efficiency and reduce channel length. The NMOS gate and the capacitor top plate is the same polysilicon gate. It is electrical isolated and works as “floating gate”. The capacitor bottom plate is the lateral diffusion region of NLDD. It works as the “control gate”. In comparing with traditional structure the cell size shrinks 40% and can be easily integrated into a standard CMOS process without additional mask.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126793378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of RF performance and reliability of 28V RF-LDMOS 28V RF- ldmos射频性能及可靠性优化
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755763
Ying Cai, hengliang Zhou, Haifeng Mo, Hu Peng, Yaohui Zhang, Jiye Yang, Jingfeng Huang, Han Yu, Junlang Li
{"title":"Optimization of RF performance and reliability of 28V RF-LDMOS","authors":"Ying Cai, hengliang Zhou, Haifeng Mo, Hu Peng, Yaohui Zhang, Jiye Yang, Jingfeng Huang, Han Yu, Junlang Li","doi":"10.1109/CSTIC.2019.8755763","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755763","url":null,"abstract":"Here is presented an optimized RF-LDMOS (Radio Frequency Lateral Double Diffused MOS) structure with double grounded G-shield and multiple drift region implants which significantly improved HCI and high RF performance especially for high frequency application. The experimental data shown both excellent HCI and high RF performance have been achieved. Measured with full load test, we have gained 1.42 W/mm and 1.36 W/mm output power density and 68.76% and 65.97% drain efficiency in 2110MHz and 2600MHz respectively. And the Idq and Rdson degradation are both less than 5% when extrapolate to 20 years.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116928727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Investigation on LDMOS Characteristics of Layout Dependence in FinFET Technology FinFET技术中布局依赖的LDMOS特性研究
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755646
Gang Wang, Byunghak Lee, Guiying Ma, Nan Wang, Mike Tang, Kellin Ding, B. Zhou, J. Ju
{"title":"Investigation on LDMOS Characteristics of Layout Dependence in FinFET Technology","authors":"Gang Wang, Byunghak Lee, Guiying Ma, Nan Wang, Mike Tang, Kellin Ding, B. Zhou, J. Ju","doi":"10.1109/CSTIC.2019.8755646","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755646","url":null,"abstract":"The characteristics of a laterally diffused metal oxide semiconductor (LDMOS) with different layout structures is investigated based on 14nm FinFET technology. The layout dependences of the breakdown voltage (BVDS), linear drain current (Idlin), on state resistance (Ron), drain cut-off current (Idoff), and Idlin degradation were studied to optimize FinFET performance with improved device structure. The overlap between N-drift region and metal gate (Lw) has a crucial impact on the breakdown voltage, Idlin, and Ron. The BVDS is 4% lower, and Ron reduced about 15% for 1x channel length device at Lw=1.8x than Lw=1x. Idoff is increased with the increase of Lw. The BVDS, Idoff, and Idlin degradation caused by hot carrier injection (HCI) are also investigated by the different overlap length of P-type well and N-drift region (Lo). With increase of Lo, the BVDS is increased and Ioff is decreased. The Idlin degradation is reduced 1.8 times by the optimization of Lo.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121372018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Interaction Between Random Telegraph Noise and Hot Carrier Ageing 随机电报噪声与热载波老化的相互作用
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755673
A. Manut, J. F. Zhang, Z. Ji, W. Zhang
{"title":"Interaction Between Random Telegraph Noise and Hot Carrier Ageing","authors":"A. Manut, J. F. Zhang, Z. Ji, W. Zhang","doi":"10.1109/CSTIC.2019.8755673","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755673","url":null,"abstract":"As downscaling reaches nanometer scale, Hot Carrier Ageing (HCA) and Random Telegraphy Noise (RTN) are two important sources of device instability. Early works typically investigate them separately and treat them as independent phenomena. In reality, however, they occur simultaneously in a device and their interaction is not fully understood. In this work, we study the impact of HCA on RTN amplitude. It is found that for devices of average RTN, HCA only has a limited effect on RTN. For devices of abnormally high RTN, however, HCA can substantially reduce the RTN. The underlying physical mechanism is explored.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132614257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An effective method to reduce bump defect is investigated 研究了一种有效的减少凹凸缺陷的方法
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755607
Xiang Guangxin, Gong Yiqi, Wei Xiang, Luo Zhi-gang, Bao Yu, Zhou Haifeng, Fang Jingxun, A. Pang
{"title":"An effective method to reduce bump defect is investigated","authors":"Xiang Guangxin, Gong Yiqi, Wei Xiang, Luo Zhi-gang, Bao Yu, Zhou Haifeng, Fang Jingxun, A. Pang","doi":"10.1109/CSTIC.2019.8755607","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755607","url":null,"abstract":"In this paper, problems and solutions for bump defect due to the stopper-SiCN layer and scrubber are investigated, and the mechanism of the defect by SiCN is clarified. In the 28 nm node flow, it is found that skipping SiCN layer scrubber and increasing NH3 flow rate and reducing pressure can effectively eliminate bump defect. In the proposed mechanism, the unsaturated bond suspension bond of Si can easily absorb a large amount of OH− plays an important role in forming bump defect, liquid line condense and residue will be effect on bump defect after scrubber. This paper analyzes this mechanism in detail.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Inversions Optimization in XOR-Majority Graphs with an Application to QCA 异或多数图的反转优化及其在QCA中的应用
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755713
Lei Shi, Zhufei Chu
{"title":"Inversions Optimization in XOR-Majority Graphs with an Application to QCA","authors":"Lei Shi, Zhufei Chu","doi":"10.1109/CSTIC.2019.8755713","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755713","url":null,"abstract":"Inversions are indispensable to build a logically complete Boolean system. However, the implementations of inversion in some nanotechnologies are expensive than the other logical operations. Therefore, the inversions optimization is of paramount interest for high-performance nanotechnology circuit design. Recently, XOR-Majority Graphs (XMGs) are used as logic representations for advanced logic synthesis. To this end, we propose an XMG optimization technique to rewrite the complemented edges while not changing its shape. The optimizations consider both majority-of-three (MAJ) nodes and exclusive-OR (XOR) nodes by using inverter propagations. The experimental results on EPFL benchmark suites show our method can achieve an average reduction of 17.3% number of inversions, which brings up to 9.8% area improvement for the implementation using Quantum-dot Cellular Automata (QCA) circuits.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126356669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Local Layout Effect Impact to Single Device in SRAM 6T Cell SRAM 6T Cell中局部布局效应对单个器件的影响
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755621
Yijun Zhang, Nan Wang, Yu Li, Yuan Wang, Xiaohua Li, Guiying Ma, Yongcheng Zhai, J. Ju
{"title":"Local Layout Effect Impact to Single Device in SRAM 6T Cell","authors":"Yijun Zhang, Nan Wang, Yu Li, Yuan Wang, Xiaohua Li, Guiying Ma, Yongcheng Zhai, J. Ju","doi":"10.1109/CSTIC.2019.8755621","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755621","url":null,"abstract":"As CMOS scaling extends into the Nano scale tech-node, designers need to not only pay attention to the device behavior impact by traditional geometric parameters, such as channel length and width; but also need to be aware on layout implementation details of the device and its surrounding neighborhood. Static Random Access Memories (SRAM) 6T cell is a basic circuit constitute by six single device, including two PMOS and four NMOS. Large SRAM arrays are widely used as cache memory in electric industries and can be applied to monitor process quality and stability in manufacture process. The device performance of single device in SRAM 6T cell determined whether a SRAM cell can function, and seriously influenced the read/write margin of it. As the single device in SRAM 6T cell up against complicated layout surroundings, their performance is largely independent of the neighborhood environment. In this paper, we will focus on three types of local layout effect to SRAM single device, including NW size effect, metal boundary effect and gate extension AA size effect. The change mode of device in SRAM circuit is analyzed and mechanisms is investigated to explain them.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115585973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effective Activating Compensation Logic for Drams in 3D-ICs 3d - ic中dram的有效激活补偿逻辑
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755615
Dingcheng Jia, Pingqiang Zhou
{"title":"Effective Activating Compensation Logic for Drams in 3D-ICs","authors":"Dingcheng Jia, Pingqiang Zhou","doi":"10.1109/CSTIC.2019.8755615","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755615","url":null,"abstract":"3D-IC is a promising solution to the “Memory Wall”. The transmission issue of data between processor and memory will be migrated in this way, and the high bandwidth can achieve further performance improvement. However, high operation temperature and long-term stress condition induce more severe Bias Temperature Instability (BTI) effect in 3D-IC. This paper explores the activation failure of DRAM caused by BTI effect in 3D stacked system which degrades circuit functionality over time. Meanwhile, additional compensation logic is proposed to compensate the sensing failure. The charge saving in memory storage cell when being activated can obtain about 15% improvement in the scenario of heavy unbalanced workload.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114830262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Significant Improvement of UTS CIS SRAM Vmin Yield by Optimizing LDD Implantation 优化LDD植入对UTS CIS SRAM Vmin产率的显著提高
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755688
Weiwei Ma, Chao Sun, Yamin Cao
{"title":"Significant Improvement of UTS CIS SRAM Vmin Yield by Optimizing LDD Implantation","authors":"Weiwei Ma, Chao Sun, Yamin Cao","doi":"10.1109/CSTIC.2019.8755688","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755688","url":null,"abstract":"55 nm UTS CIS SRAM Mbist Loss under 1 V is reduced significantly (2%) by optimizing LDD (lightly doped drain) implantation process, including adjusting twist angle, codoping Carbon and Indium. Besides, better leakage performance has also been achieved under these optimized LDD implantation condition. Furthermore, Vmin yield could also be improved by increasing the ratio of core n-type device speed vs core p-type device.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thickness Dependence Characteristics of High-κ Al2O3 Based Metal-Insulator-Metal Antifuse 高κ Al2O3基金属-绝缘子-金属抗熔断器的厚度依赖特性
2019 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2019-03-18 DOI: 10.1109/CSTIC.2019.8755789
Min Tian, H. Zhong
{"title":"Thickness Dependence Characteristics of High-κ Al2O3 Based Metal-Insulator-Metal Antifuse","authors":"Min Tian, H. Zhong","doi":"10.1109/CSTIC.2019.8755789","DOIUrl":"https://doi.org/10.1109/CSTIC.2019.8755789","url":null,"abstract":"In this paper, a new metal-insulator-metal (MIM) antifuse with the high κ Al2O3 deposited by atomic layer deposition (ALD) as the dielectric has been successfully fabricated. On this high κ antifuse structure, the very low on-state resistance was obtained under certain programming conditions. It is the first time that the antifuse on-state resistance has been found decreasing along with the increase of dielectric film thickness, which is attributed to a large current overshoot during breakdown, and the current overshoot is found to be larger with thicker Al2O3 dielectric.","PeriodicalId":113297,"journal":{"name":"2019 China Semiconductor Technology International Conference (CSTIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127066886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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