International Conference on Parallel Processing, 2004. ICPP 2004.最新文献_第4页

Evaluating the scalability of Java event-driven Web servers 评估Java事件驱动Web服务器的可伸缩性

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.34

Vicencc Beltran, David Carrera, J. Torres, E. Ayguadé

引用次数: 24

Using hardware operations to reduce the synchronization overhead of task pools 使用硬件操作来减少任务池的同步开销

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327927

Ralf Hoffmann, Matthias Korch, T. Rauber

引用次数: 8

Runtime system for autonomic rescheduling of MPI programs 自主重调度MPI程序的运行时系统

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327898

C. Du, Sudeshna Ghosh, S. Shankar, Xian-He Sun

引用次数: 10

Architectural characterization of an XML-centric commercial server workload 以xml为中心的商业服务器工作负载的体系结构特征

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327935

P. Apparao, R. Iyer, R. Morin, Naren Nayak, M. Bhat, D. Halliwell, W. Steinberg

{"title":"Architectural characterization of an XML-centric commercial server workload","authors":"P. Apparao, R. Iyer, R. Morin, Naren Nayak, M. Bhat, D. Halliwell, W. Steinberg","doi":"10.1109/ICPP.2004.1327935","DOIUrl":"https://doi.org/10.1109/ICPP.2004.1327935","url":null,"abstract":"As XML (extensible markup language) rapidly emerges as the standard for information storage and communication, it becomes increasingly important to understand its architectural characteristics and performance implications. In This work, our goal is to characterize a representative XML-based server in a managed runtime environment such as Java. Based on detailed measurements on an Intel/spl reg/ XeonTM processor-based commercial server running a real-world XML-based server workload, we start by looking at symmetric multiprocessor (SMP) scaling characteristics and the benefits of hyper-threading technology. Using performance monitoring events provided on the processor, we present an overview of the architectural characteristics (such as clocks per instruction (CPI), cache miss rates, memory/bus utilization, branch behavior and efficiency). Using profiling tools like Intel/spl reg/ VTuneTM performance analyzer, we map these architectural/performance characteristics to the various components of application execution - helping us identify hot spots and propose potential enhancements to code generation and application software. We believe that the information presented Are useful in understanding the XML processing characteristics and may serve as a useful first step to identifying potential hardware/software optimizations for improved future performance.","PeriodicalId":106240,"journal":{"name":"International Conference on Parallel Processing, 2004. ICPP 2004.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123227083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Complexity results and heuristics for pipelined multicast operations on heterogeneous platforms 异构平台上管道组播操作的复杂度结果和启发式算法

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327931

Olivier Beaumont, Arnaud Legrand, L. Marchal, Y. Robert

引用次数: 12

Parallel software for inductance extraction 电感提取并行软件

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327946

H. Mahawar, V. Sarin

{"title":"Parallel software for inductance extraction","authors":"H. Mahawar, V. Sarin","doi":"10.1109/ICPP.2004.1327946","DOIUrl":"https://doi.org/10.1109/ICPP.2004.1327946","url":null,"abstract":"The next generation VLSI circuits will be designed with millions of densely packed interconnect segments on a single chip. Inductive effects between these segments begin to dominate signal delay as the clock frequency is increased. Modern parasitic extraction tools to estimate the onchip inductive effects with high accuracy have had limited impact due to large computational and storage requirements. This work describes a parallel software package for inductance extraction called ParIS, which is capable of analyzing interconnect configurations involving several conductors within reasonable time. The main component of the software is a novel preconditioned iterative method that is used to solve a dense complex linear system of equations. The linear system represents the inductive coupling between filaments that are used to discretize the conductors. A variant of the fast multipole method is used to compute dense matrix-vector products with the coefficient matrix. ParIS uses a two-tier parallel formulation that allows mixed mode parallelization using both MPIand OpenMP. An MPI process is associated with each conductor. The computation within a conductor is parallelized using OpenMP. The parallel efficiency and scalability of the software is demonstrated through experiments on the IBM p690 and Intel and AMD Linux clusters. These experiments highlight the portability and efficiency of the software on multiprocessors with shared, distributed, and distributed-shared memory architectures.","PeriodicalId":106240,"journal":{"name":"International Conference on Parallel Processing, 2004. ICPP 2004.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Robust resource allocation for sensor-actuator distributed computing systems 传感器-执行器分布式计算系统的鲁棒资源分配

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327919

Shoukat Ali, A. A. Maciejewski, H. Siegel, Jong-Kook Kim

{"title":"Robust resource allocation for sensor-actuator distributed computing systems","authors":"Shoukat Ali, A. A. Maciejewski, H. Siegel, Jong-Kook Kim","doi":"10.1109/ICPP.2004.1327919","DOIUrl":"https://doi.org/10.1109/ICPP.2004.1327919","url":null,"abstract":"This research investigates two distinct issues related to a resource allocation: its robustness and the failure rate of the heuristic used to determine the allocation. The target system consists of a number of sensors feeding a set of heterogeneous applications continuously executing on a set of heterogeneous machines connected together by high-speed heterogeneous links. There are number of quality of service (QoS) constraints that must be satisfied. A heuristic failure occurs if the heuristic cannot find an allocation that allows the system to meet its QoS constraints. The system is expected to operate in an uncertain environment where the workload, i.e., the load presented by the set of sensors, is likely to change unpredictably, possibly invalidating a resource allocation that was based on the initial workload estimate. The focus of this paper is the design of a static heuristic that: (a) determines a robust resource allocation, i.e., a resource allocation that maximizes the allowable increase in workload until a run-time reallocation of resources is required to avoid a QoS violation, and (b) has a very low failure rate. This study proposes a heuristic that performs well with respect to the failure rates and robustness to unpredictable workload increases. This heuristic is, therefore, very desirable for systems where low failure rates can be a critical requirement and where unpredictable circumstances can lead to unknown increases in the system workload.","PeriodicalId":106240,"journal":{"name":"International Conference on Parallel Processing, 2004. ICPP 2004.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116589646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Faucets: efficient resource allocation on the computational grid 水龙头:计算网格上有效的资源分配

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327948

L. Kalé, Sameer Kumar, M. Potnuru, J. Desouza, S. Bandhakavi

{"title":"Faucets: efficient resource allocation on the computational grid","authors":"L. Kalé, Sameer Kumar, M. Potnuru, J. Desouza, S. Bandhakavi","doi":"10.1109/ICPP.2004.1327948","DOIUrl":"https://doi.org/10.1109/ICPP.2004.1327948","url":null,"abstract":"The idea of a \"computational grid\" suggests that high end computational power can be thought of as a utility, similar to electricity or water. Making this metaphor work requires a sophisticated \"power distribution\" infrastructure. We present the Faucets framework that aims at providing (a) user-friendly compute power distribution across the grid, (b) market-driven selection of compute servers for each job, resulting in effective utilization of resources across the grid, and (c) improved utilization within individual compute servers. Utilization of individual compute servers is improved by the notions of adaptive jobs and smarter job schedulers. Server selection is facilitated by quality-of-service (QoS) contracts for parallel jobs. Market efficiencies are then attained by a bidding and evaluation system that makes the compute servers compete for every job by submitting bids, thus transforming the computational grid into a free market. Job submission and monitoring is simplified by several tools and databases within the Faucets system. We describe the overall architecture of the system. All the essential components of the system have been implemented, which are described In the work. We also discuss ongoing work and future research issues.","PeriodicalId":106240,"journal":{"name":"International Conference on Parallel Processing, 2004. ICPP 2004.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116640382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

Adaptive data partition for sorting using probability distribution 基于概率分布的自适应数据分区排序

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327928

Xipeng Shen, C. Ding

引用次数: 8

A future of parallel computer architectures 并行计算机体系结构的未来

International Conference on Parallel Processing, 2004. ICPP 2004. Pub Date : 2004-08-15 DOI: 10.1109/ICPP.2004.1327896

M. Hill

引用次数: 0