CPSS Transactions on Power Electronics and Applications最新文献

An Improved Finite Control Set Model Predictive Control Based on a Novel Dual-Port Three-Level Inverter 基于新型双端口三电平逆变器的改进有限控制集模型预测控制

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-12-01 DOI: 10.24295/CPSSTPEA.2024.00027

Guifeng Wang;Xin Yuan;Yunhui Jiang;Jianfei Wang;Fei Wang;Zhan Liu

{"title":"An Improved Finite Control Set Model Predictive Control Based on a Novel Dual-Port Three-Level Inverter","authors":"Guifeng Wang;Xin Yuan;Yunhui Jiang;Jianfei Wang;Fei Wang;Zhan Liu","doi":"10.24295/CPSSTPEA.2024.00027","DOIUrl":"https://doi.org/10.24295/CPSSTPEA.2024.00027","url":null,"abstract":"In response to the high cost and large size issues associated with traditional back-to-back three-level inverters, this paper proposes a novel dual-port three-level inverter (DP-TLI) that simplifies the system structure through the utilization of switch multiplexing. Based on the proposed inverter topology, a time-sharing coordination finite control set model predictive control (TSC-FCS-MPC) strategy is developed. The strategy, grounded in the concept of time-sharing control, incorporates a coordinated approach within a two-cycle control loop. During the first cycle, the primary control objective is to optimize the output current of the upper port, with the selection of the optimal vector centered around this goal. Subsequently, the lower port's output is coordinated through control, leveraging the unique aspects of switch multiplexing and the redundancy in switch states inherent in the proposed topology. In the second cycle, the emphasis is reversed, with the optimization of the lower port's output current taking precedence, while the upper port is subjected to coordinated control. The implementation of this method significantly enhances the quality of the output current and the overall efficiency of the system. The viability and effectiveness of both the proposed topology and the control strategy are confirmed through simulation and experimental results.","PeriodicalId":100339,"journal":{"name":"CPSS Transactions on Power Electronics and Applications","volume":"9 4","pages":"430-442"},"PeriodicalIF":0.0,"publicationDate":"2024-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10829717","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Sensorless Control of Permanent Magnet Synchronous Motor Based on Tracking Differentiator-Frequency-Locked Loop 基于跟踪微分器锁频环的永磁同步电机无传感器控制

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-12-01 DOI: 10.24295/CPSSTPEA.2024.00025

Sibo Wan;Huimin Wang;Yun Zuo;Gaoli Guo;Xinglai Ge

{"title":"Sensorless Control of Permanent Magnet Synchronous Motor Based on Tracking Differentiator-Frequency-Locked Loop","authors":"Sibo Wan;Huimin Wang;Yun Zuo;Gaoli Guo;Xinglai Ge","doi":"10.24295/CPSSTPEA.2024.00025","DOIUrl":"https://doi.org/10.24295/CPSSTPEA.2024.00025","url":null,"abstract":"Sensorless control technique is regarded as the enabler of the reliability improvements for interior permanent magnet synchronous motor (IPMSM) drives. However, the conventional estimation schemes by using the phase-locked loop (PLL) and the frequency-locked loop (FLL) may experience undesired accuracy under acceleration and deceleration cases (ADCs). To address this, a speed estimation scheme by combining a closed-loop active flux observer (CLAFO) with a tracking differentiator-based frequency-locked loop (TD-FLL) was proposed in this paper. Starting from a brief introduction of the conventional PLL performance analysis with - and FLLADCs based estimation schemes, a detailed is provided. Accordingly, an estimation scheme based on the TD-FLL is elaborated. Considering the performance of the proposed TD-FLL scheme is adversely affected by various disturbances, a CLAFO is carefully designed to improve the disturbance immunity of the proposed TD-FLL scheme. Extensive experimental tests are conducted to verify the effectiveness of the proposed TD-FLL scheme under different test cases.","PeriodicalId":100339,"journal":{"name":"CPSS Transactions on Power Electronics and Applications","volume":"9 4","pages":"454-464"},"PeriodicalIF":0.0,"publicationDate":"2024-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10829711","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Randomized Self-Structuring Adaptive Neuro-Fuzzy Based Induction Motor Drives with Optimized FOPI Gains 具有优化FOPI增益的随机自结构自适应神经模糊感应电机驱动

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-12-01 DOI: 10.24295/CPSSTPEA.2024.00026

Pudari Mahesh;Sabha Raj Arya

{"title":"Randomized Self-Structuring Adaptive Neuro-Fuzzy Based Induction Motor Drives with Optimized FOPI Gains","authors":"Pudari Mahesh;Sabha Raj Arya","doi":"10.24295/CPSSTPEA.2024.00026","DOIUrl":"https://doi.org/10.24295/CPSSTPEA.2024.00026","url":null,"abstract":"This paper describes the randomized evolving Takagi-Sugeno (ReTSK)-adaptive neuro-fuzzy (ANF) estimation algorithm and optimized fractional-order proportional integral (FOPI) controller are integrated with parameter adaptive indirect vector control (PA-IVC) for induction motor drives performance enhancement. For appropriate slip-speed tuning and field orientation, the machine learning-based ReTSK-ANF approach is proposed for the estimation of induction motor parameters and sensorless speed. The optimized FOPI speed and current regulators are employed in PA-IVC to generate the reference signals with minimized error for encountering manual tuning and reduce the overshoot with less settling time. A metaheuristic algorithm of Gazelle optimization algorithm (GOA) is imposed, to obtain the optimal weight, biases, membership functions (MFs), and MF rules in the predicative model of ReTSK-ANF for desired parameter estimation and optimal gains of FOPI for performance enhancement. Statistical metrics are carried out to examine the performance of ReTSK forecasting model. The metrics are mean square error (MSE), root mean square error (RMSE), mean error (ME), and error of standard deviation (ESD) as reportd during the training stage, were 3.33e-3, 3.41e-2, 1.92e-3, 3.37e-2, and during the testing stage 3.67e-3, 3.47e-2, 1.91e-3, 3.42e-2. This will confirm that the ReTSK-ANF estimator will achieve significant improvement in the estimation of parameters and closely follow the reference. Meanwhile, the optimized FOPI gains performance is analyzed using time response analysis.","PeriodicalId":100339,"journal":{"name":"CPSS Transactions on Power Electronics and Applications","volume":"9 4","pages":"465-475"},"PeriodicalIF":0.0,"publicationDate":"2024-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10829710","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Frequency Multiplier Algorithm Based Fundamental Active Current Extraction and Phase Locked Loop for the Control of 3-Phase Shunt Active Power Filter 基于倍频算法的基态有源电流提取和锁相环控制三相并联有源电力滤波器

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-10-18 DOI: 10.24295/CPSSTPEA.2024.00022

Amit V. Sant;Arpitkumar J. Patel;Josep M. Guerrero

{"title":"Frequency Multiplier Algorithm Based Fundamental Active Current Extraction and Phase Locked Loop for the Control of 3-Phase Shunt Active Power Filter","authors":"Amit V. Sant;Arpitkumar J. Patel;Josep M. Guerrero","doi":"10.24295/CPSSTPEA.2024.00022","DOIUrl":"https://doi.org/10.24295/CPSSTPEA.2024.00022","url":null,"abstract":"Control of shunt power active filter (SAPF) necessitates estimation of the fundamental active component (FAC) of load current and unit voltage templates (UVTs). In this paper, a frequency multiplier based FAC and UVT extractor is proposed, wherein the \u0000<tex>$alpha-beta$</tex>\u0000 quantities of load current and supply voltage undergo frequency multiplier action to obtain the respective components with fundamental frequency four times the power frequency. With the band pass filtering of these signals, the components corresponding to four times the power frequency are determined. Thus obtained current components are further processed to extract the FAC of load current. Similarly obtained voltage signals are used by the synchronous reference frame theory based phase locked loop for accurate UVT extraction with the help of the designed synchronizing logic. The comparative analysis performed using an experimental setup demonstrates faster dynamic response and accurate estimation with a developed extractor compared to earlier reported schemes. The performance of SAPF controlled with the proposed extraction algorithm is investigated in PSIM software. Further, experimental validation is also presented. The SAPF operation with the proposed control scheme ensures unity power-factor operation and adherence to total harmonic distortion (THD) limits by drawing sinusoidal currents from the grid.","PeriodicalId":100339,"journal":{"name":"CPSS Transactions on Power Electronics and Applications","volume":"9 4","pages":"384-394"},"PeriodicalIF":0.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10723227","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Configurable Multi Input Port Hybrid Inverter Topology With Quadrupled Voltage Gain for PV and Hybrid Applications 一个可配置的多输入端口混合逆变器拓扑与四倍电压增益的PV和混合应用

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-10-18 DOI: 10.24295/CPSSTPEA.2024.00020

Baibhav Kumar Gupta;Aashish Kumar;K. Ramachandra Sekhar

{"title":"A Configurable Multi Input Port Hybrid Inverter Topology With Quadrupled Voltage Gain for PV and Hybrid Applications","authors":"Baibhav Kumar Gupta;Aashish Kumar;K. Ramachandra Sekhar","doi":"10.24295/CPSSTPEA.2024.00020","DOIUrl":"https://doi.org/10.24295/CPSSTPEA.2024.00020","url":null,"abstract":"The presented work demonstrates the three-port inverter configuration for a quadrupled reduction in the operating DC bus voltage compared to conventional inverter topology. Thus, the proposed configuration consists the single inversion stage and operates with single or multiple sources. Irrespective of the source connected at input ports, the three inverters in the tri-inverter configuration synthesize the 512 switching combinations and spread across 61 voltage space locations to realize the load space vector. The switching states are segregated from the space spread not only to realize the maximum voltage gain but also to eliminate the common mode voltage during common DC source operations. In the case of common DC source operation, the CMV eliminated switching combinations ensures the elimination of circulating current with minimum compromise of the voltage gain. The improved voltage gain and eliminated circulating current guarantees the maximum energy yield from source and improved reliability of the converter compared to the conventional inverter. The proposed converter's efficacy and realized space vector switching states in terms of realizable four times voltage gain and the elimination of intra-inverter circulating currents are validated experimentally with single and multiple sources.","PeriodicalId":100339,"journal":{"name":"CPSS Transactions on Power Electronics and Applications","volume":"9 4","pages":"361-372"},"PeriodicalIF":0.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10723225","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Synchronization Stability of Hybrid Power Systems Integrated with Grid-Forming Inverters and Grid-Following Inverters 并网逆变器与随网逆变器集成的混合电力系统同步稳定性研究

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-10-18 DOI: 10.24295/CPSSTPEA.2024.00024

Dian Lu;Jingrong Yu;Xiawei Lu;Jiaqi Yu

引用次数: 0

An Improved Minor Loop Gain Criterion and Stability Estimation for Multi-Inverters Paralleled System 一种改进的多逆变器并联系统小回路增益准则及稳定性估计

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-10-18 DOI: 10.24295/CPSSTPEA.2024.00023

Yuhan Duan;Pingjuan Ge;Hailiang Xu;Hongbin Lin

{"title":"An Improved Minor Loop Gain Criterion and Stability Estimation for Multi-Inverters Paralleled System","authors":"Yuhan Duan;Pingjuan Ge;Hailiang Xu;Hongbin Lin","doi":"10.24295/CPSSTPEA.2024.00023","DOIUrl":"https://doi.org/10.24295/CPSSTPEA.2024.00023","url":null,"abstract":"With the increasing popularity of new energy integration, the parallel operation of multiple inverters in power systems has become commonplace. Traditional theories and methods for analyzing power system stability face challenges in high-proportion new energy systems. Additionally, existing inverter analysis methods are inadequate for directly addressing multi-inverters paralleled system, resulting in unclear instability mechanisms and uncertain operational stability. To tackle these issues, this paper focuses on systems with multiple parallel LCL-type inverters and proposes an improved minor loop gain criterion (IMLG). Unlike traditional impedance ratio criteria, this improved criterion fully integrates considerations such as inverter capacity, short-circuit ratio, and other pertinent factors affecting system stability. Furthermore, treating each inverter as a subsystem by equivalent the grid conductance to the inverter side, this criterion accurately identifies the primary inverter responsible for system instability. Finally, case and experimental studies are employed to verify the correctness of the theoretical analysis and demonstrate the effectiveness of the improved stability criterion.","PeriodicalId":100339,"journal":{"name":"CPSS Transactions on Power Electronics and Applications","volume":"9 4","pages":"416-429"},"PeriodicalIF":0.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10723224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Method for Measuring Radiated Common Mode Current of Isolated Power Converters 一种测量隔离型电源变换器辐射共模电流的新方法

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-10-18 DOI: 10.24295/CPSSTPEA.2024.00021

Qingbin Chen;Qinwen Yang;Jianxin Shi;Shaohui Xu

引用次数: 0

Enhancing the Perturbation Injection Capabilities of Grid-Connected Converters With Asymmetric Signals 利用非对称信号增强并网变流器的扰动注入能力

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-08-30 DOI: 10.24295/CPSSTPEA.2024.00017

Jules Mace;Andrea Cervone;Drazen Dujic

{"title":"Enhancing the Perturbation Injection Capabilities of Grid-Connected Converters With Asymmetric Signals","authors":"Jules Mace;Andrea Cervone;Drazen Dujic","doi":"10.24295/CPSSTPEA.2024.00017","DOIUrl":"https://doi.org/10.24295/CPSSTPEA.2024.00017","url":null,"abstract":"Impedance identification is an important tool for the evaluation of grid-converter interactions, and it is based on the injection of a controlled small signal perturbation and in the analysis of the corresponding system response. Using already installed grid-connected converters as perturbation sources offers the advantage of avoiding additional dedicated hardware, but faces some implementation challenges caused by the limited voltage reserve that is normally available in such equipment. To overcome this limitation, this work presents perturbation injection signals that, by considering asymmetric voltage limits, can make the best use of the limited voltage reserve available in the system. The developed approach is first presented for a periodic multi-tone perturbation injection, and then it is extended for narrow-band and wide-band perturbations. Analytical, numerical and experimental results prove that the proposed solution can provide perturbation injections with considerably higher magnitudes compared to other conventional approaches, which makes it ideal to enhance the perturbation injection capabilities of existing grid-connected converters.","PeriodicalId":100339,"journal":{"name":"CPSS Transactions on Power Electronics and Applications","volume":"9 3","pages":"345-359"},"PeriodicalIF":0.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10661297","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142376686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A New 7, 15 and 31-level Modular Reduced Switch Multilevel Inverter with Gating Signal Generation Using Digital Output Pins 采用数字输出引脚产生门控信号的新型7、15和31电平模块化简化开关多电平逆变器

CPSS Transactions on Power Electronics and Applications Pub Date : 2024-08-30 DOI: 10.24295/CPSSTPEA.2024.00018

Amit V. Sant;Kashyap Patoliya

{"title":"A New 7, 15 and 31-level Modular Reduced Switch Multilevel Inverter with Gating Signal Generation Using Digital Output Pins","authors":"Amit V. Sant;Kashyap Patoliya","doi":"10.24295/CPSSTPEA.2024.00018","DOIUrl":"https://doi.org/10.24295/CPSSTPEA.2024.00018","url":null,"abstract":"This paper proposes a reduced switch modular multilevel inverter (RSM-MLI) requiring eight, thirteen, and fifteen switches per phase for 7-level, 15-level, and 31-level output voltages, respectively. For the generation of 7-level, 15-level, and 31-level output voltages, the proposed MLI employs two, three, and four designed modules, each comprising switches, diodes, and a DC source, respectively. The interconnection of modules results in the generation of unipolar staircase voltage. Further, an H-bridge inverter (HBI) facilitates DC-AC conversion. With modular construction, the levels can be easily increased in the proposed topology by adding extra modules. The merits of the proposed topology are highlighted through a comparative analysis. The higher switch count in MLI necessitates the use of multiple digital signal processors (DSPs), thereby complicating the gating circuitry. To simplify the gating requirements, this paper utilizes the digital output pins in a DSP, which are far higher in number than the PWM pins, for gate pulse generation. This negates the needs of multiple DSPs. The operation of the developed experimental prototype of the proposed 7-level, 15-level, and 31-level RSM-MLI, controlled through the digital output pins of a DSP, is analyzed for steady-state and dynamic conditions.","PeriodicalId":100339,"journal":{"name":"CPSS Transactions on Power Electronics and Applications","volume":"9 4","pages":"373-383"},"PeriodicalIF":0.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10661295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0