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A Convolutional Neural Network Pipeline For Multi-Temporal Retinal Image Registration. 基于卷积神经网络管道的多时间视网膜图像配准。
International SoC Design Conference. International SoC Design Conference Pub Date : 2021-10-01 Epub Date: 2021-11-25 DOI: 10.1109/isocc53507.2021.9613906
Chi-Jui Ho, Yiqian Wang, Junkang Zhang, Truong Nguyen, Cheolhong An
{"title":"A Convolutional Neural Network Pipeline For Multi-Temporal Retinal Image Registration.","authors":"Chi-Jui Ho,&nbsp;Yiqian Wang,&nbsp;Junkang Zhang,&nbsp;Truong Nguyen,&nbsp;Cheolhong An","doi":"10.1109/isocc53507.2021.9613906","DOIUrl":"https://doi.org/10.1109/isocc53507.2021.9613906","url":null,"abstract":"<p><p>A sequence of images is usually captured to observe the change of health status in medical diagnosis. However, an image sequence taken over year usually suffers from severe deformation, making it time-consuming for physicians to match corresponding patterns. In this paper, we propose a coarse-to-fine pipeline for retinal image registration based on convolutional neural network. By leveraging the three components of the pipeline: feature matching, outlier rejection, and local registration, we recover the deformation and accurately align multi-temporal image sequences. Experimental results show that the proposed network is robust to severe deformation as well as illumination and contrast variations. With the proposed registration pipeline, the change of image patterns over time can be identified through visual analysis.</p>","PeriodicalId":93770,"journal":{"name":"International SoC Design Conference. International SoC Design Conference","volume":"2021 ","pages":"27-28"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9359415/pdf/nihms-1823143.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"40601506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparative analysis of FinFET and Planar MOSFET SRAMs FinFET与平面MOSFET sram之比较分析
International SoC Design Conference. International SoC Design Conference Pub Date : 2020-01-01 DOI: 10.1109/ISOCC50952.2020.9333122
K. Pradeep, B. Mohith, P. ManjunathK., S. SunitaM.
{"title":"Comparative analysis of FinFET and Planar MOSFET SRAMs","authors":"K. Pradeep, B. Mohith, P. ManjunathK., S. SunitaM.","doi":"10.1109/ISOCC50952.2020.9333122","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333122","url":null,"abstract":"","PeriodicalId":93770,"journal":{"name":"International SoC Design Conference. International SoC Design Conference","volume":"116 1","pages":"11-12"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74911699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.5-V sub-mW energy-efficient receiver in 0.18-μm CMOS for IoT applications 用于物联网应用的0.5 v亚毫瓦节能接收器，采用0.18 μm CMOS
International SoC Design Conference. International SoC Design Conference Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799835
Tse-Wei Wang, Yi-Lin Tsai, Chong-Rong Lee, Fu-Lian Hung, Tsung-Hsien Lin
{"title":"A 0.5-V sub-mW energy-efficient receiver in 0.18-μm CMOS for IoT applications","authors":"Tse-Wei Wang, Yi-Lin Tsai, Chong-Rong Lee, Fu-Lian Hung, Tsung-Hsien Lin","doi":"10.1109/ISOCC.2016.7799835","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799835","url":null,"abstract":"A 0.5-V differential BPSK (D-BPSK) receiver (RX) realized in 0.18-μm CMOS is presented in this paper. This RX adopts the injection-locking technique to demodulate the received signal. The core of this RX is an injection-locked oscillator which converts the input phase transition to envelope variation for demodulation. This work is fabricated in TSMC 0.18-μm CMOS technology. The proposed RX consumes 0.97 mW from a 0.5-V supply. The sensitivity is −45 dBm. At 10-Mbps data rate, the energy efficiency is 97 pJ/b.","PeriodicalId":93770,"journal":{"name":"International SoC Design Conference. International SoC Design Conference","volume":"88 1","pages":"157-158"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79733793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoder 166.7 Mhz 1920×1080 60fps H.264/SVC视频解码器
International SoC Design Conference. International SoC Design Conference Pub Date : 2011-11-01 DOI: 10.1109/ISOCC.2011.6138764
Seunghyun Cho, Seongmo Park, N. Eum
{"title":"A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoder","authors":"Seunghyun Cho, Seongmo Park, N. Eum","doi":"10.1109/ISOCC.2011.6138764","DOIUrl":"https://doi.org/10.1109/ISOCC.2011.6138764","url":null,"abstract":"In this paper, a hardware design of an H.264/SVC video decoder is presented. Large size inter-coded pictures in a high frame rate require a high external memory bandwidth in decoding process. Inter-layer predictions of SVC further increase data transfer from or to an external memory. A cache-based motion compensation to sufficiently reduce overhead cycles for external SDRAM access and the bandwidth requirement is proposed. Much variation of macroblock processing cycles for CABAC decoding is another obstacle to design a SVC video decoder with macroblock based pipelining scheme. A frame level delaying method is proposed to remove the cycle variations, so that the decoder works with a steady throughput. The proposed SVC decoder shows HD1080p 60fps of decoding capability operating at 166.7MHz.","PeriodicalId":93770,"journal":{"name":"International SoC Design Conference. International SoC Design Conference","volume":"22 1","pages":"278-281"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86299763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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